Ultrahigh-Bandwidth Low-Latency Reconfigurable Memory Interconnects by Wavelength Routing

Abstract

Researchers at the University of California, Davis, have developed a memory system that uses optical interconnects.

Full Description

The technology encompasses low latency memory systems and a novel silicon photonics (SiPh) architecture using Wavelength Division Multiplexing based optical interconnects.The silicon photonic interconnects enable optical parallelism and wavelength routing to reduce contention in the entire path from a processor to a memory subarray. The low latency architecture can include three pieces: a contention-less optical data plane, a low-bandwidth electrical control plane, and fine-grained memory banks with integrated photonics. In the data plane, the arrayed wavelength grating router (AWGR)-based optical interconnect can provide a dedicated data path from every requester to every memory bank, with no intermediate buffering, to reduce the queuing and interconnect latency. In the control plane, a low-bandwidth electrical or optical interconnect can communicate the addresses and commands between processors and memory and coordinate the time that a processor sends or receives data. The fine-grained memory banks (also referred to as microbanks) can be directly accessed by the memory controller to allow for massive amounts of parallelism.

Applications

• Low Latency Memory System Architecture 
• Silicon Photonics (SiPh) with space saving scalability 
• Processor and Memory Interconnect Solution 
• Suitable for processor, memory, and system designers and manufacturers

Features/Benefits

• High parallelism data communication in memory systems 
• Fast throughput and low energy data communication 
• Replaces conventional electrical interconnects

Patent Status