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An Implantable Electrocorticogram (ECoG)-Brain-Computer Interface System for Restoring Lower Extremity Movement and Sensation

A fully implantable brain-computer interface (BCI) with onboard processing to control a robotic gait exoskeleton as a walking aid for individuals with chronic spinal cord injury (SCI). This technology would alleviate SCI patient’s dependence on wheel chairs, reducing the risk of secondary medical complications that account for an estimated $50 billion/year in healthcare costs.

Robust High Speed Analog QAM Demodulator for Advanced Wireless Applications

Wireless applications are witnessing major advancement in fields like virtual reality and cellular phones, thus requiring much higher data transfer speed. This technology is a novel architecture for wireless receivers that accommodates such targeted high data rates, while maintaining a cost efficient design; power efficient while still utilizing simple circuits design, through replacing complicated digital blocks with innovative analog ones.

Very High Energy Density Silicide-Air Primary Batteries

UCLA researchers in the Department of Materials Science and Engineering, and Department of Chemistry and Biochemistry have developed a new family of silicide based anode materials for high energy density metal-air primary batteries.

Strained Voltage-Controlled Magnetic Memory Elements and Devices

Researchers under Kang Wang at UCLA have verified through computational calculations that manipulation of strain in materials used in and around the magnetic tunnel junction interface (MEJ) can be used to increase the magnitude of voltage controlled magnetic anisotropy (VCMA) and subsequently lower the required switching voltage required in MEJ based memory systems.

Anti-Ferromagnetic Magneto-Electric Spin-Orbit Read Logic

UCLA researchers in the department of Electrical Engineering have developed a novel magetoelectric device for use as a spin transistor.

A Single-Shot Network Analysis Method For The Characterization Of Opto-Electronic And Electrical Devices And Systems

UCLA researchers in the Department of Electrical Engineering have developed a single-shot network analysis method that can perform both time and frequency domain measurements of non-linear behavior of various optical or electrical devices and systems within significantly reduced test time.

Hollow Plastic Waveguide ("Wave Cable") Based High Speed And Low Power Data Center Inter-Server Link

UCLA researchers in the department of Electrical Engineering have developed a novel and inexpensive plastic interconnect for high efficiency communication within data centers.

Arbitrary Channel Responses Learning Mechanism In Multi-Band Rf-Interconnect (MRFI) For Wireline Communication

UCLA researchers have developed a novel hardware-efficient carrier synchronization technique for multiband RF interconnect systems.

Respiratory Monitor For Asthma And Other Pulmonary Conditions

A patch sensor that is able to continuously monitor breathing rate and volume to diagnose pulmonary function and possibly predict and possibly prevent fatal asthma attacks.

Millimeter-Wave CMOS Transceiver with PCB Antenna for Contactless Wave-Connectors

UCLA researchers in the Department of Electrical Engineering have developed a novel interconnect solution that allows for high data bandwidth, compact form-factor, reduced power consumption and universal compatibility to existing interconnect practices.

A simple, accurate and inexpensive device pointing system using head tilt gesturing

Current device pointing systems, which control the movement of cursors on screens, suffer from several drawbacks which often preclude their use by individuals with special needs or medical conditions. This UCI invention describes a simple, inexpensive “head mouse” that, in combination with proprietary software, tracks the position of the head relative to the body, allowing for full control of a pointing device.

A Circuit-Based Scalable and Low-Complex Optical Datacenter Network

The ever‐increasing bandwidth requirements of modern datacenters have led researchers to propose networks based upon optical circuit switches, but these proposals face significant deployment challenges. In particular, previous proposals dynamically configure circuit switches in response to changes in workload, requiring network‐wide demand estimation, centralized circuit assignment, and tight time synchronization between various network elements— resulting in a complex and unwieldy control plane. Moreover, limitations in the technologies underlying the individual circuit switches restrict both the rate at which they can be reconfigured and the scale of the network that can be constructed; a new approach is necessary.

Resistive Memory Write and Read Assistance Using Negative Differential Resistance Devices

UCLA researchers in the Department of Electrical Engineering have developed a new design of read and write circuitry using negative differential resistance devices to improve the performance of resistive memories.

Data Shepherding: Cache Design For Future Large Scale Chips

The ability of a central processing unit to store frequently-used data in nearby, easily accessible cache data banks has revolutionized computational performance, though their effective implementation in multicore processors has become a technological challenge. Researchers at UCI have developed a new means of data caching that is fully applicable to multicore processors, and offers reduced memory access time over standard techniques.

Automated Reconstruction Of The Cardiac Chambers From MRI

This is a fast, fully automated method to accurately model a patient’s left heart ventricle via machine learning algorithms.

Monitor Alarm Fatigue Allevation By SuperAlarms - Predictive Combination Of Alarms

UCLA researchers in the Department of Neurosurgery have developed a method that is capable of mining a collection of monitor alarms to search for specific combinations of encoded monitor alarms to predict certain adverse event, such as in-hospital code blue arrests or other target events.

Mechanical Process For Creating Particles Using Two Plates

UCLA researchers in the Department of Chemistry and Biochemistry & Physics and Astronomy have developed a novel method to lithograph two polished solid surfaces by using a simple mechanical alignment jig with piezoelectric control and a method of pressing them together and solidifying a material.

Two-Step Processing With Vapor Treatment Of Thin Films Of Organic-Inorganic Perovskite Materials

Prof. Yang and colleagues have developed a novel method of preparing organic-inorganic thin films using a solution process followed by vapor treatment, presenting a low-cost, high-performance solution method of producing optoelectronic devices.

Two-Dimensional Patterning Of Integrated Circuit Layer By Tilted Ion Implantation

The proliferation of information technology (IT) – which has had dramatic economic and social impact – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of transistors on an IC “chip” doubles every two years. In other words, the primary reason for increasing the number of components (transistors) on a chip is to lower the manufacturing cost per component. Increased integration also has the benefits of providing for improved system performance and energy efficiency. Therefore, the semiconductor industry has steadily scaled linear transistor dimensions, by a factor of approximately 0.7´ with every new generation of manufacturing technology, over the past 50 years. The most advanced chips today comprise over 10 billion transistors within an area of a few cm2. The pace of IC technology advancement has slowed down for the most recent generations, however, due to fundamental limits of the conventional photolithographic patterning process. Double-patterning techniques such as “self-aligned double patterning (SADP)” are used today to pattern IC layers with sub-45 nm feature size and minimum pitch, well below the wavelength of light used in the photolithography process. These techniques involve many additional steps, including extra lithography and etching processes, however, which result in increased cost of patterning.  To address the issue of increasing patterning cost, researchers at the University of California, Berkeley have developed a new method for patterning an IC layer with minimum feature pitch smaller than the minimum pitch of the photolithographic process and with minimum feature size smaller than the lithographic resolution limit, using well-established planar processing techniques.  A significant advantage of this new method is that it can be used to define two-dimensional layout patterns, which can provide for more compact integrated circuits.

Interposers Made From Nanoporous Anodic Films

Many electronic devices rely on integrated circuits, whereby different electrical components are incorporated into a single chip and connected to one another through interposers. Researchers at UCI and Integra have developed a new interposer that allows for a high density of electrical connections, and whose fabrication is cheaper and easier than conventional methods.

Synthesis Technique to Achieve High-Anisotropy FeNi

Researchers at the University of California, Davis have developed an innovative synthesis approach to achieve high anisotropy L1 FeNi by combining physical vapor deposition and a high speed rapid thermal annealing (RTA).

Wearable Monitoring System Better Understands Autism Spectrum Disorder

Researchers at the University of California, Davis have developed a wearable monitoring system to better understand the emotional dysregulation that an individual with an autism spectrum disorder (ASD) may encounter.

Terahertz (THz) Interconnect Semiconductor with High Energy and Bandwidth Density

Researchers at the University of California, Davis have developed a sub-THz interconnect semiconductor that can operate at high bandwidth densities and high-energy efficiencies.

RF-Powered Micromechanical Clock Generator

Realizing the potential of massive sensor networks requires overcoming cost and power challenges. When sleep/wake strategies can adequately limit a network node's sensor and wireless power consumption, then the power limitation comes down to the real-time clock (RTC) that synchronizes sleep/wake cycles. With typical RTC battery consumption on the order of 1µW, a low-cost printed battery with perhaps 1J of energy would last about 11 days. However, if a clock could bleed only 10nW from this battery, then it would last 3 years. To attain such a clock, researchers at UC Berkeley developed a mechanical circuit that harnesses squegging to convert received RF energy (at -58dBm) into a local clock while consuming less than 17.5nW of local battery power. The Berkeley design dispenses with the conventional closed-loop positive feedback approach to realize an RCT (along with its associated power consumption) and removes the need for a sustaining amplifier altogether. 

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