Error-Triggered Learning For Efficient Memristive Neuromorphic Hardware
Tech ID: 33936 / UC Case 2021-744-0
Brief Description
An
innovative learning algorithm that enables efficient online training of spiking
neural networks on memristive neuromorphic hardware.
Full Description
This
technology introduces a local, gradient-based, error-triggered learning
algorithm with online ternary weight updates for multilayer Spiking Neural
Networks (SNNs). It leverages memristive neuromorphic hardware for efficient
computation, significantly reducing energy consumption while maintaining high
performance levels. The algorithm is complemented by a hardware architecture
designed for low-power operation, incorporating memristive crossbar arrays and
peripheral circuitry optimized for online training in neuromorphic systems.
Suggested uses
- Development of energy-efficient neuromorphic chips for AI applications.
- Advancements in lifelong learning systems for robotics and autonomous machines.
- Enhancements in edge computing devices, reducing reliance on cloud-based computations.
- Innovations in low-power, high-performance computing for wearable technology and IoT devices.
- Applications in real-time
data processing and decision-making systems requiring minimal energy
consumption
Advantages
- Enables online training directly on neuromorphic hardware, eliminating the need for off-chip learning.
- Significantly more energy-efficient than traditional methods, with over 80x energy improvement observed.
- Designed for low-power operation using subthreshold regime technology in a standard 180 nm CMOS process.
- Supports lifelong learning capabilities through efficient implementation of learning dynamics as synaptic plasticity.
- Addresses the von-Neumann
bottleneck by reducing data shuttling between memory and processing units.
Patent Status
United States Of America |
Published Application |
2022109593 |
05/25/2022 |
2021-744 |
|
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