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New Technique to Reduce Register File Accesses in GPUs

Prof. Nael Ghazaleh and Hodjat Asghari Esfeden from the University of California, Riverside have developed Breathing Operand Windows (BOW), an enhanced GPU pipeline and operand collector technique that supports bypassing register file accesses and instead passes values directly between instructions within the same window. While this baseline design can only bypass register reads, they also introduce an improved design capable of bypassing unnecessary write operations to the RF. Compiler optimizations help guide the write-back destination of operands depending on whether they will be reused to further reduce the write traffic. The BOW microarchitecture reduces RF dynamic energy consumption by 55%, while at the same time increases overall performance by 11%, with a modest overhead of 12KB of additional storage which is ~4% of the RF size. Fig 1: shows the dynamic energy normalized to the baseline GPU for BOW-WR across fifteen different benchmarks. The small segments on top of each bar represent the overheads of the structures added by the idea. Dynamic energy savings in Fig 1 are due to the reduced number of accesses to the register file as BOW-WR shields the RF from unnecessary read and write operations.  

Advanced On-Chip Thermal Sensing

Prof. Albert Wang and his colleagues from the University of California, Riverside have developed a novel in-hole PN diode thermal sensor that can be readily made in commercial IC production processes. The technology is advantageous over current thermal sensors because the in-hole diode is designed to take up a minimal amount of space while it ensures high-resolution thermal sensing. With the new concept validated experimentally, the new in-hole diode sensor can be a potential solution to achieving full-chip dynamic thermal mapping with a fine spatial resolution for accurate real-time chip-scale thermal management for future ICs. Fig 1: TCAD simulation shows desired I-V-T behaviors for the new in-hole diode thermal sensor across a wide temperature range.

Advanced Electrostatic Discharge Protection

Prof. Albert Wang and colleagues from the University of California, Riverside have developed an effective and reliable method for designing an internally distributed CDM ESD protection network. This technology works by having the ESD protection network distributed inside the silicon substrate. Existing CDM ESD protection methods use external pad-based ESD protection to channel discharge in a pathway known as “from-external-to-internal” which leads to CDM ESD failures. This technology is superior to current methods because the discharge is directed “from internal-to-external” and solves the fundamental issues that cause existing CDM ESD protection methods to fail. Fig 1: Illustration of the pad-based global ESD protection network on an IC chip where ESD protection devices are connected to each pad to ensure an ESD discharging path between pads on a chip.

Integration And Mass Transfer Of Microleds

Brief description not available

Bottom-Up Synthesis Of Nanoporous Graphene With Emergent Electronic States

Nanoporous graphene (NPG) is unique in that it exhibits both electronic functionality as a tunable semiconductor and mechanical functionality as a tunable molecular filter membrane. Combining these properties into a single atomically-thin, mechanically robust platform makes NPG an excellent candidate for electronically active nanosieve applications such as sequencing, sensing, ion transport, gas separation, and water purification. The incorporation of nanoscale pores into a sheet of graphene allows it to switch from an impermeable semimetal to a semiconducting nano-sieve.    The performance of nanoporous graphene is highly dependent on the periodicity and reproducibility of pores at the atomic level. The utility of this material, however, hinges on the ability to induce periodic, atomically-precise nanopores and to tailor their precise dimensions and electronic properties. Top-down lithographic approaches have proven to be challenging due to poor structural control at the atomic level and because they typically produce random, imprecise pores within a material that remains semi-metallic. A disadvantage of the few reported bottom-up synthesized NPGs is that the constituent nanoribbons are wide gap semiconductors.    Using a bottom-up synthesis, UC Berkeley researchers have created a fully conjugated nanoporous graphene through a single, mild annealing step following an initial polymer formation. They found emergent interface-localized electronic states within the bulk band gap of the graphene nanoribbon that hybridize to yield a dispersive two-dimensional low-energy band of states. The localization of these 2D states around pores makes this material particularly attractive for applications requiring electronically sensitive molecular sieves.

Development of a CMOS-Compatible, Nano-photonic, Laser

Researchers at the University of California, Davis have developed a new class of lasers and amplifiers that uses a CMOS-compatible electronics platform - and can also be applied to nano-amplifiers and nano-lasers applications.

New Spin Current-Based Memory Devices and Switches

Prof. Jing Shi and his colleagues from the University of California, Riverside have developed two new applications to utilize spin current in electronic devices. The first is a pure spin current switch that allows for the manipulation of pure spin current in electronic devices by allowing the user to switch between an “on” and “off” state. The device includes a first metal layer, a magnetic insulator layer, and a second metal layer. This technology controls the flow of information by switching the direction of magnetization of the middle layer. Since spin current does not require electricity, the spin current switch holds an innovative promise for the future of the way electronic devices channel current. The second is a non-volatile random access memory (RAM) device capable of using spin current to reduce electricity consumption. The technology can transmit information through electrical insulators, where the flow of information can be switched “off” by applying a magnetic field. The “on” and “off” states are two non-volatile memory states that can be stored as the magnetization direction of the magnetic insulator layer. This technology holds promise for a new generation of RAM technology that is not limited by memory bottleneck.  Fig. 1: A schematic illustration of a spin current valve. Top: The switch in the "on" position. Bottom: The switch in the "off" position.  

Scalable Manufacturing of Copper Nanocomposites with Tunable Properties

UCLA researchers in the Department of Mechanical and Aerospace Engineering have developed a cost-effective method to produce copper-based nanocomposites with excellent mechanical, electrical and thermal properties.

Flexible Microfluidic Sensors for Curved Surfaces

UCLA researchers in the Department of Mechanical and Aerospace Engineering have developed flexible tactile sensors for curved surfaces that are robust against fatigue and suitable for robotic applications.

Low Energy and Noise Sub-Sampling Phase-Locked Loop

Phase locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency, or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Researchers at the University of California, Davis have invented a novel, sub-sampling phase-locked, loop (SSPLL) that uses a sub-sampling lock detector (SSLD) to monitor the harmonic selected by the SSPLL. This technology requires lower energy consumption and reduces signal noise.

Diamond On Nanopatterned Substrates

UCLA researchers in the Department of Materials Science and Engineering have developed a nanofabrication method for improving the thermal properties of polycrystalline diamond films grown by chemical vapor deposition.

Techniques for Creation and Insertion of Test Points for Malicious Circuitry Detection

Researchers led by Dr. Potkonjak from the UCLA Department of Computer Science have developed a technique to detect hardware Trojans in integrated circuits.

Magnetoelectric Device with Two Dielectric Barriers

UCLA researchers in the Department of Electrical and Computer Engineering have developed a magnetoelectric memory device that uses two dielectric barriers for improved voltage-controlled magnetic anisotropy (VCMA) and tunnel magnetoresistance (TMR) properties.

An Improved On-Chip Crosstalk Noise Model

Researchers led by Jason Cong from the Department of Computer Science at UCLA have developed an improved on-chip crosstalk noise model to optimize integrated circuit design.

Selective Deposition Of Diamond In Thermal Vias

UCLA researchers in the Department of Materials Science & Engineering have developed a new method of diamond deposition in integrated circuit vias for thermal dissipation.

Wafer Bonding for Embedding Active Regions with Relaxed Nanofeatures

An alternative method, using wafer bonding, to connect relaxed nanostructures in the active region with separately grown material.

A Nonvolatile Magnetoelectric Random Access Memory Circuit

UCLA researchers in the Department of Electrical Engineering have developed a nonvolatile random-access memory circuit (MeRAM) that is very dense, fast, and consumes extremely low power.

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