An Design Automation Methodology Based On Graph Neural Networks To Model The Integrated Circuits And Mitigate The Hardware Security Threats

Brief Description

An innovative design automation methodology leveraging graph neural networks to enhance integrated circuit security by mitigating hardware threats and protecting intellectual property.

Full Description

This technology introduces a novel automated methodology utilizing graph neural networks (GNN) to model integrated circuits (IC) and address hardware security threats such as Hardware Trojans (HT) and intellectual property (IP) piracy. By converting circuit designs into graph-based representations, this approach enables the detection and mitigation of security threats through advanced machine learning techniques. The methodology encompasses tools for HT detection, localization, and removal, as well as IP piracy detection, without imposing manual feature engineering or significant design overhead.

Suggested uses

· Electronic Design Automation (EDA) tools for secure IC design.

· Hardware security assessment and verification platforms.

· IP protection and anti-piracy solutions for semiconductor industries.

· Secure system-on-chip (SoC) design and manufacturing.

· Defense and aerospace applications requiring high-security IC components

Advantages

· Automates the detection and mitigation of hardware security threats.

· Scalable to large and complex circuit designs.

· Capable of identifying unknown HT and IP piracy instances.

· Reduces reliance on trusted reference designs for HT detection.

· Minimizes manual workload for feature engineering and security analysis.

· Does not add hardware overhead to the design for IP piracy detection

Patent Status

Patent Pending