Enabling Partial Soft-Switching Within Regulating Switched Capacitor Converter

Tech ID: 34184 / UC Case 2025-188-0

Patent Status

Patent Pending

Brief Description

High-conversion-ratio power converters used in compact Point-of-Load (PoL) applications, such as data centers or portable electronics, often face the challenge of large size and weight due to the necessary energy-storage components, particularly flying capacitors, while also struggling with switching losses that reduce efficiency. This innovation, developed by UC Berkeley researchers, addresses these issues with a novel regulating hybrid switched-capacitor (HSC) power converter topology referred to as a "Dual Inductor Switching Bus Converter" (DISB converter). The DISB converter combines an initial 2:1 switched-capacitor conversion stage with a Symmetric Dual-Inductor Hybrid (SDIH) conversion stage, capitalizing on the benefits of both. The initial 2:1 voltage reduction significantly reduces the overall volume and weight of the flying capacitors, while the SDIH stage contributes a reduced component count and an excellent switch stress figure of merit. Crucially, a proposed auxiliary circuit block enables near-zero-voltage conditions (partial soft-switching) within the initial 2:1 stage, which significantly improves the converter's overall efficiency.

Suggested uses

  • High conversion ratio Point-of-Load (PoL) power conversion in space-constrained applications.

  • Power supply solutions for data centers and server racks where size and weight are critical.

  • Integration into portable electronics and other weight-sensitive devices.

  • Replacing traditional power converters to achieve higher power density and efficiency.

Advantages

  • Reduced Volume/Weight of flying capacitors due to the initial 2:1 voltage reduction stage.

  • Significantly Improved Efficiency through an auxiliary circuit block that enables near-zero-voltage (partial soft-switching) in the 2:1 stage.

  • Reduced Component Count offered by the Symmetric Dual-Inductor Hybrid (SDIH) conversion stage.

  • Excellent Switch Stress Figure of Merit provided by the SDIH stage.

  • Suitable for high conversion ratio applications.

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Inventors

  • Pilawa-Podgurski, Robert C.N.

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