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Browse Category: Semiconductors > Design and Fabrication

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Blade Coating On Nanogrooved Substrates Yielding Aligned Thin Films Of High Mobility Semiconductin Polymers

An alternative method of alignment specifically developed for field-effect transistors of organic electronics.

Wafer Scale Growth Of Large Arrays Of Perovskite Micro-Plate Crystals For Functional Electronics And Optoelectronics

UCLA researchers in the Department of Chemistry and Biochemistry and the Department of Materials Science and Engineering have developed a method to grow patterned perovskite micro-plate crystal arrays for functional electronic and optoelectronic applications.

Power Distribution within Silicon Interconnect Fabric

UCLA researchers in the Department of Electrical Engineering have developed a novel method of powering systems on silicon interconnect fabrics for integration of packageless processors.

A Method For Fabricating Nitride Layers

A method for fabricating a semiconductor substrate with improved quality of the subsequently deposited semiconductor layers.

Fabrication Of 1D Sinusoidal Silicon Dioxide Substrate

UCLA researchers in the department of Electrical Engineering have developed a novel fabrication process for microstrip patch antennas with size reduction and dual band capabilities.

Graphene-Polymer Nanocomposite Incorporating Chemically Doped Graphene-Polymer Heterostructure for Flexible and Transparent Conductive Films

UCLA researchers in the Department of Electrical Engineering have invented a novel graphene-polymer nanocomposite material for flexible transparent conductive electrode (TCE) applications.

Periodically Rippled Antenna

UCLA researchers in the Department of Electrical Engineering have designed a periodically-rippled microstrip patch antenna for wireless communication systems.

Anti-Ferromagnetic Magneto-Electric Spin-Orbit Read Logic

UCLA researchers in the department of Electrical Engineering have developed a novel magetoelectric device for use as a spin transistor.

Full Color Quantum Dot Patterning Via Soft Lithography

UCLA researchers in the Department of Chemistry and Biochemistry have developed a novel quantum dot patterning method via soft lithography. It allows cost-effective, large-scale and high resolution full-color quantum dots patterning, which will revolutionize the nanoelectronics and QD-based display industries.

Polarization Standing Wave Cavity Assisted By Anisotropic Structures

Researchers in the Department of Electrical Engineering have developed a cavity demonstrating resonance through polarization standing waves.

Repeatable Ultra-Fast Low Jitter Spark Gap

UCLA researchers in the Department of Physics have developed a spark gap using a high dielectric material for pulsed laser applications.

Transparent Bulk Photoluminescent Quantum Dots/Polymer Nanocomposite

UCLA researchers in the Department of Materials Science and Engineering have developed highly transparent, photoluminescent nanocomposites containing record-high levels of quantum dots.

III-Nitride Vertical Transistor with Ion Implantation Formed Aperture Region

Researchers at the University of California, Davis have developed a method of fabricating a III-nitride vertical transistor with aperture region formed using ion implantation as a path to achieve selective area doping.

Resistive Memory Write and Read Assistance Using Negative Differential Resistance Devices

UCLA researchers in the Department of Electrical Engineering have developed a new design of read and write circuitry using negative differential resistance devices to improve the performance of resistive memories.

Data Shepherding: Cache Design For Future Large Scale Chips

The ability of a central processing unit to store frequently-used data in nearby, easily accessible cache data banks has revolutionized computational performance, though their effective implementation in multicore processors has become a technological challenge. Researchers at UCI have developed a new means of data caching that is fully applicable to multicore processors, and offers reduced memory access time over standard techniques.

A Hybrid Silicon Laser-Quantum Well Intermixing Wafer Bonded Integration Platform

An approach for integrating InP-based photonic devices together with low loss silicon photonics and complementary metal-oxide-semiconductor (CMOS) electronics.

Internal Heating for Ammonothermal Growth of Group-III Nitride Crystals

A new process for heating vessels used in the ammonothermal growth of group-III nitrides.

Current to Voltage Converter for High-Speed Optical Fiber Communications

The exponential increase in internet traffic due to the increased availability of internet access as well as high demand activities (such as movie streaming) presents an enormous challenge to infrastructure in handling this increasing amount of data. The UCI researchers have developed an ultra-broadband transimpedance amplifier (TIA), which is a key component for coupling high-speed optical fiber to conventional metal wiring. The silicon-based circuit is capable of 50 Gbps data transfer, representing a 25% increase over other, state of the art devices.

Mechanical Process For Creating Particles Using Two Plates

UCLA researchers in the Department of Chemistry and Biochemistry & Physics and Astronomy have developed a novel method to lithograph two polished solid surfaces by using a simple mechanical alignment jig with piezoelectric control and a method of pressing them together and solidifying a material.

Two-Step Processing With Vapor Treatment Of Thin Films Of Organic-Inorganic Perovskite Materials

Prof. Yang and colleagues have developed a novel method of preparing organic-inorganic thin films using a solution process followed by vapor treatment, presenting a low-cost, high-performance solution method of producing optoelectronic devices.

Trademark: Flexible Fan Out Wafer Processing And Structure: Flextrate

UCLA researchers in the Department of Electrical Engineering have invented a novel biocompatible flexible device fabrication method using fan-out wafer level processing (FOWLP).

A Structure For Increasing Mobility In A High-Electron-Mobility Transistor

A technique that results in a significant increase of electron mobility and sheet charge density at small channel thickness.

Two-Dimensional Patterning Of Integrated Circuit Layer By Tilted Ion Implantation

The proliferation of information technology (IT) – which has had dramatic economic and social impact – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of transistors on an IC “chip” doubles every two years. In other words, the primary reason for increasing the number of components (transistors) on a chip is to lower the manufacturing cost per component. Increased integration also has the benefits of providing for improved system performance and energy efficiency. Therefore, the semiconductor industry has steadily scaled linear transistor dimensions, by a factor of approximately 0.7´ with every new generation of manufacturing technology, over the past 50 years. The most advanced chips today comprise over 10 billion transistors within an area of a few cm2. The pace of IC technology advancement has slowed down for the most recent generations, however, due to fundamental limits of the conventional photolithographic patterning process. Double-patterning techniques such as “self-aligned double patterning (SADP)” are used today to pattern IC layers with sub-45 nm feature size and minimum pitch, well below the wavelength of light used in the photolithography process. These techniques involve many additional steps, including extra lithography and etching processes, however, which result in increased cost of patterning.  To address the issue of increasing patterning cost, researchers at the University of California, Berkeley have developed a new method for patterning an IC layer with minimum feature pitch smaller than the minimum pitch of the photolithographic process and with minimum feature size smaller than the lithographic resolution limit, using well-established planar processing techniques.  A significant advantage of this new method is that it can be used to define two-dimensional layout patterns, which can provide for more compact integrated circuits.

Interleaved 3D On-Chip Differential Inductor And Transformer

UCLA researchers in the Department of Electrical Engineering have developed an interleaved three-dimensional (3D) on-chip differential inductors and transformers used in silicon based radio frequency/millimeter wave integrated circuits

On-Chip Tunable Artificial Dielectrics

UCLA Researchers in the Department of Electrical Engineering have developed and reduced-to-practice an innovative method for making chips with tunable dielectrics so the wavelength of RF signals can be modified to achieve frequency tuning effects without effecting noise interference.

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