The proliferation of information technology (IT) – which has had dramatic economic and social impact – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of transistors on an IC “chip” doubles every two years. In other words, the primary reason for increasing the number of components (transistors) on a chip is to lower the manufacturing cost per component. Increased integration also has the benefits of providing for improved system performance and energy efficiency. Therefore, the semiconductor industry has steadily scaled linear transistor dimensions, by a factor of approximately 0.7´ with every new generation of manufacturing technology, over the past 50 years. The most advanced chips today comprise over 10 billion transistors within an area of a few cm2. The pace of IC technology advancement has slowed down for the most recent generations, however, due to fundamental limits of the conventional photolithographic patterning process. Double-patterning techniques such as “self-aligned double patterning (SADP)” are used today to pattern IC layers with sub-45 nm feature size and minimum pitch, well below the wavelength of light used in the photolithography process. These techniques involve many additional steps, including extra lithography and etching processes, however, which result in increased cost of patterning. To address the issue of increasing patterning cost, researchers at the University of California, Berkeley have developed a new method for patterning an IC layer with minimum feature pitch smaller than the minimum pitch of the photolithographic process and with minimum feature size smaller than the lithographic resolution limit, using well-established planar processing techniques. A significant advantage of this new method is that it can be used to define two-dimensional layout patterns, which can provide for more compact integrated circuits.