|Patent Cooperation Treaty||Published Application||WO 2022/225698||10/27/2022||2021-149|
Additional Patent Pending
With the two-dimensional scaling of silicon field-effect transistors reaching fundamental limits, new functional improvements to transistors, as well as novel computing paradigms and vertical device integration at the architecture-level, are currently under intense study. Gate oxides play a critical role in this endeavor, as it’s a common performance booster for all devices, including silicon, new channel materials with potential for higher performance, and even materials suitable for three-dimensional integrated transistors.
With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage.
To pursue these performance gains, UC Berkeley researchers invented a new heterostructure insulator material where: 1) the material possesses specific ferroic order such as ferroelectricity/anti-ferroelectricity or a mixture of both; 2) the overall dielectric property such as the permittivity is determined by the stacking order of different layers rather than exact volume fraction of the constituents; and 3) the material is composed of one or several repetition of ultra thin superlattice periods ranging from a few angstroms to 3 nm.
This material could be used as a gate oxide for all transistors in general. In addition, it can also be used in DRAM memory.
This heterostructure will provide very large permittivity or in some cases negative permittivity that will enhance the total permittivity of a stack made of this specific heterostructure and another dielectric, ferroelectric, anti-ferroelectric, multiferroic insulator or a semiconductor.