Ultra-Low-Voltage Clock Generation Architecture

Background

Over the past 5 to 7 years, non-overlapping (NOV) clock phase generators have conventionally relied on downstream, dedicated auxiliary logic—such as cross-coupled SR latch delay blocks. While effective at nominal voltages, these additional stages create severe power overhead and fail under ultra-low-voltage (ULV) constraints due to reduced transistor gain and output swing. Recent advances attempted to integrate NOV phase generation directly within ring oscillators to improve energy efficiency. However, topologies relying on bootstrap architectures or heavy transistor stacking (e.g., laddered inverters) remain restricted to minimum operating voltages ranging from 0.5V to 1.0V. Present implementations lack the ability to directly produce non-overlapping clock phases at sub-100 mV supply levels without incurring high area and power costs from auxiliary phase-generation circuits.

Technology Description

To help address these challenges, researchers at UC Santa Cruz (UCSC) have developed a new ring oscillator architecture with a series of delay cells that directly generates non-overlapping clock phases without requiring downstream auxiliary circuits. Each delay cell, preferably utilizing a stacked-inverter structure, includes an output node and internal pull-up and pull-down nodes. The internal nodes are cross-coupled across adjacent delay cells to form a primary oscillation loop alongside first and second auxiliary oscillation loops. By intentionally omitting a cross-coupling connection at a single stage, a relative phase shift is produced between the auxiliary loops. This creates an enveloping effect that outputs direct non-overlapping clock phases. Additionally, the dead time between phases is tunable by adjusting transistor sizing (beta-ratio) within the delay cells, enabling functional operation at sub-100 mV supply voltage.

Applications

• energy-autonomous edge, IoT devices
• ULV power converters and charge pumps
• sub-threshold biomedical sensors / wearables

Features/Benefits

• Second-order stacked-inverter delay cells drastically increase voltage transfer characteristic steepness and effective DC gain, overcoming known intrinsic gain reductions at extreme sub-threshold voltages e.g. sub-100mV.
• Direct generation of non-overlapping clock phases via internal auxiliary loops eliminates the need for power-hungry external SR-latch phase generators or auxiliary logic stages.
• Enables precise dead-time control while maintaining a stable main-loop oscillation frequency.

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