Reducing Electrical Current Variations in Phase-Locked Loop Systems

Tech ID: 32424 / UC Case 2021-623-0


Researchers at the University of California, Davis have developed a method of eliminating electrical current mismatches in the charge pumps of phase-locked loops (PLL) systems - thereby increasing their power efficiency and phase detection capabilities.

Full Description

Telecommunication systems and other signal processing applications often require frequency generation or matching. Traditional phase-frequency detector (PFD)-based phase-locked looping (PLL) is the standard technology currently for generating and synthesizing accurate frequencies. Sub Sampling Phase Locked Loop (SSPLL) technologies use a charge pump to help control the regulation of the electrical current sent into the filtering loop of the SSPLL. However, these charge pumps are highly susceptible to small voltage fluctuations that can reduce their locking range and lead to large output signal distortions. A method of regulating charge pump current would allow for the creation of a much more efficient SSPLL design – resulting in a better locking range, improved gain, and reduced power consumption. 

Researchers at the University of California Davis have developed a method of compensating for mismatched current in charge pumps. This new, SSPLL technology includes a sub-sampling phase detector (SSPD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a frequency-locked loop - which ensures a desired output frequency. It also implements a charge pump current mismatch compensation structure containing a “dummy” charge pump and feedback loops. The feedback loops sense the output voltage of the charge pump and provide compensating current to both the actual charge pump and the “dummy” pump – thus eliminating the electrical current mismatch. As a result, the voltage control locking range improves from 50% of the supply voltage to 75% - enabling the SSPLL to match frequencies more quickly. The signal gain improves as well, as degeneration associated with the phase detector is eliminated. Power consumption is also reduced, as the simplified voltage control design allows the supply voltage to be as low as 0.5V. This improvement is particularly important when operating at high frequencies. This technology is a significant improvement over existing SSPLL systems, and can be implemented in a wide variety of electronic circuits.


  • Telecommunications, computer hardware, and other signal processing systems operating at high frequencies


  • An improved locking range provides for faster phase matching in SSPLL systems
  • Reduced power consumption, especially at high frequencies (30-1000 GHz) 
  • Can be operated at under 0.5V supply voltage

Patent Status

Country Type Number Dated Case
United States Of America Published Application 20230370072 11/16/2023 2021-623
Patent Cooperation Treaty Published Application 2022/125188 07/21/2022 2021-623


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  • Momeni, Omeed
  • Wang, Hao

Other Information


Phase-locked loop, sub-sampling phase-locked loop, SSPLL, analog circuit, electrical current mismatch

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