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Precision Graphene Nanoribbon Wires for Molecular Electronics Sensing and Switch

The inventors have developed a highly scalable multiplexed approach to increase the density of graphene nanoribbon- (GNR) based transistors. The technology forms a single device/chip (scale to 16,000 to >1,000,000 parallel transistors) on a single integrated circuit for single molecule biomolecular sensing, electrical switching, magnetic switching, and logic operations. This work relates to the synthesis and the manufacture of molecular electronic devices, more particularly sensors, switches, and complimentary metal-oxide semiconductor (CMOS) chip-based integrated circuits.Bottom-up synthesized graphene nanoribbons (GNRs) have emerged as one of the most promising materials for post-silicon integrated circuit architectures and have already demonstrated the ability to overcome many of the challenges encountered by devices based on carbon nanotubes or photolithographically patterned graphene. The new field of synthetic electronics borne out of GNRs electronic devices could enable the next generation of electronic circuits and sensors.  

Compact Ion Gun for Ion Trap Surface Treatment in Quantum Information Processing Architectures

Electromagnetic noise from surfaces is one of the limiting factors for the performance of solid state and trapped ion quantum information processing architectures. This noise introduces gate errors and reduces the coherence time of the systems. Accordingly, there is great commercial interest in reducing the electromagnetic noise generated at the surface of these systems.Surface treatment using ion bombardment has shown to reduce electromagnetic surface noise by two orders of magnitude. In this procedure ions usually from noble gasses are accelerated towards the surface with energies of 300eV to 2keV. Until recently, commercial ion guns have been repurposed for surface cleaning. While these guns can supply the ion flux and energy required to prepare the surface with the desired quality, they are bulky and limit the laser access, making them incompatible with the requirements for ion trap quantum computing.To address this limitation, UC Berkeley researchers have developed an ion gun that enables in-situ surface treatment without sacrificing high optical access, enabling in situ use with a quantum information processor.

Scalable Manufacturing of Copper Nanocomposites with Tunable Properties

UCLA researchers in the Department of Mechanical and Aerospace Engineering have developed a cost-effective method to produce copper-based nanocomposites with excellent mechanical, electrical and thermal properties.

Thermodynamic Integration Simulation Method for Filling Molecular Enclosures Using Spliced Soft-Core Interaction Potential

Researchers have developed a simulation method to determine the properties of molecular enclosures based on slow growth thermodynamic integration (SGTI).

Method to Fabricate Josephson Junctions

Brief description not available

Method For Superconducting Tunnel Junction Fabrication

In recent years, superconducting tunnel junctions have become a viable technology for a range of cryogenic applications. Superconducting tunnel junction — also known as a superconductor–insulator–superconductor tunnel junction (SIS) — is an electronic device consisting of two superconductors separated by a thin layer of insulating material. Current passes through the junction via the process of quantum tunneling. These devices have a wide range of applications, including high-sensitivity detectors of electromagnetic radiation, magnetometers, high speed digital circuit elements, and quantum computing circuits. Normal-insulating-superconducting (NIS) junctions have been used as on-chip quantum refrigerators and more recently as bulk cryogenic coolers. Both SIS and NIS technologies require pristine dielectric barriers limited to a thickness of a few nanometers. These barriers are typically fabricated using thermal oxidation of Al or Al alloys using a controlled combination of temperature, partial pressure of oxygen, and time. Unfortunately, the diffusive nature of thermal oxidation can lead to point defects in the tunnel barrier that affect junction quality and limit device performance.

Vertical Heterostructures for Transistors, Photodetectors, and Photovoltaic Devices

The Duan group at UCLA has developed a high current density vertical field-effect transistor (VFET) that benefits from the strengths of the incorporated layered materials yet addresses the band gap problem found in current graphene technologies.

Magnetically Controlled Casting Process

Brief description not available

Formation of Polymers on Nanostructures Under X-ray Irradiation

First time demonstration of enhanced formation of polymers on nanostructures under X-ray irradiation.

Improved Mechanical Contact Reliability and Energy Efficiency for CMOS Applications

In order to overcome fundamental energy efficiency limits of CMOS technology, micro-electro-mechanical (MEM) relay technologies are now being investigated for ultra-low-power digital integrated circuit (IC) applications. High relay endurance (exceeding 10^14 ON/OFF switching cycles) is required for relay-based ICs to be viable, and has been a major challenge due to stiction and wear. Researchers at UC Berkeley have developed an efficient way to reduce contacts aging, stiction, and oxidation. The researchers have shown that contacts can be made to be very reliable with very low resistance. To date, a contact resistance of 85.2 kohms has been measured at room temperature and suggests the possible use of these contacts for relay-based integrated circuits, which typically requires contact resistances less than 100 kohms. Further work will include coating optimization, surface roughness analysis, dynamic measurements for contact aging evaluation, thermal analysis, extraction of the effective contact area, and advanced current transport modeling.

Low Cost, Low-Temperature Polycrystalline Semiconductor Films for Solar Cells and Large Scale Integrated Circuits

  In the manufacture of very large scale integrated circuits, polycrystalline-silicon (poly-Si) films are typically formed directly by low- pressure chemical vapor deposition (LPCVD) at temperatures above 600C, using silane as the precursor gas. Use of such a high process temperature renders this approach unsuitable for formation of poly-Si films on low-cost glass and plastic substrates and on substrates with completed CMOS integrated circuits. Various other techniques have been attempted, with less than ideal results, toward crystallizing amorphous silicon films without subjecting the material to excessive temperatures for the given application. Accordingly, a need exists for a method of readily forming polycrystalline films without subjecting the substrate to high temperatures, or requiring the use of complex processing steps. Researchers at UC Berkeley have developed a technology that enables the forming of polycrystalline semiconductor at low temperatures and without the use of complex processing steps. The technology allows for production of a continuous polycrystalline silicon film with excellent physical and electrical properties.  The result is a low-temperature, low-cost substrates such as glass and plastic, which is extremely important for the development and commercialization of solar cells, thin film transistors, and micro-electromechanical systems (MEMS).  

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