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Detection of single ionizing particles at rates approaching the gigahertz (GHz) range per channel has potential for applications in medical imaging and treatment as well as particle and nuclear physics. Current ionizing particle detection systems detect with maximum frame rates of ~500 MHz. As accelerators (e.g. XFELs) are upgraded to deliver trains of pulses at faster rates, detection systems will need to keep pace. Methods and devices that can detect at GHz rates will be required to meet the demands of modern societal needs and equipment.

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UCLA researchers in the Department of Materials Science and Engineering have developed a nanofabrication method for improving the thermal properties of polycrystalline diamond films grown by chemical vapor deposition.

UCLA researchers in the Department of Materials Science & Engineering have developed a new method of diamond deposition in integrated circuit vias for thermal dissipation.

Fabricating materials from naturally occurring proteins that are inherently biocompatible enables the resulting material to be easily integrated with many downstream applications, ranging from batteries to transistors. In addition, protein-based materials are also advantageous because they can be physically tuned and specifically functionalized. Inventors have developed protein-based material from structural proteins such as reflectins found in cephalopods, a molluscan class that includes cuttlefish, squid, and octopus. In a space dominated by artificial, man-made proton-conducting materials, this material is derived from naturally occurring proteins.

A low-cost solution to robust electronic packaging of 3-D MEMS devices using micro-glassblown “bubble-shaped” structures.

UCLA researchers in the Department of Chemistry and Biochemistry & Physics and Astronomy have developed a novel method to lithograph two polished solid surfaces by using a simple mechanical alignment jig with piezoelectric control and a method of pressing them together and solidifying a material.

UCLA researchers in the Department of Electrical Engineering have developed a system that can receive RF waves in different frequency bands, from different directions, and with different polarizations to maximize energy harvested from ambient radio-frequency signals.

Realizing the potential of massive sensor networks requires overcoming cost and power challenges. When sleep/wake strategies can adequately limit a network node's sensor and wireless power consumption, then the power limitation comes down to the real-time clock (RTC) that synchronizes sleep/wake cycles. With typical RTC battery consumption on the order of 1µW, a low-cost printed battery with perhaps 1J of energy would last about 11 days. However, if a clock could bleed only 10nW from this battery, then it would last 3 years. To attain such a clock, researchers at UC Berkeley developed a mechanical circuit that harnesses squegging to convert received RF energy (at -58dBm) into a local clock while consuming less than 17.5nW of local battery power. The Berkeley design dispenses with the conventional closed-loop positive feedback approach to realize an RCT (along with its associated power consumption) and removes the need for a sustaining amplifier altogether. 

Two of the leading materials considered for use in post silicon n-channel regions of planar-FETs and finFETs are SiGe and InGaAs, as both of these alternatives contain high intrinsic electron mobilities. A broader range of channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be atomic layer deposited (ALD) or self-limiting chemical vapor deposited (CVD) on multiple materials and crystallographic faces. The existing silicon ALD process is not self-limiting.

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This invention utilizes standard printed circuit board (PCB) fabrication technology to create a novel high-quality factor (Qu) continuously-tunable resonator and filter. The inherent benefits of the proposed design are: 1) flexibility in choosing various types of tuning components (e.g. solid-state, ferroelectric, and radio frequency microelectromechanical systems (RF MEMS) varactors), 2) compared to traditional cavity tunable resonators, the initial starting frequency is primarily determined by the tuning element as opposed to precise assembly techniques, and 3) industry-standard PCB substrates with commercially-available tuning components are used, thereby facilitating high-volume manufacturing, ease of integration with other RF front-end components and lower fabrication costs. A tunable resonator and two-pole bandpass filter with solid-state varactors are designed and fabricated to experimentally validate the approach. The resonator surpasses the state-of-the-art with a frequency tuning range of 0.5–1.2 GHz (tuning ratio of 2.4 : 1) and a Qu of 82–197. The bandpass filter exhibits frequency tuning of 0.57-1.17 GHz, insertion loss of 4.9-1.9 dB and a 3-dB bandwidth of 2-8 %. Lastly, an RF MEMS varactor enabled tunable resonator based on the same design further shows Quof 240 at 6.6 GHz.

Modern semiconductor detectors have been developed for sensing light, X-rays and charged particles. Such devices have established broad applications because of their reliability, and compactness. However, they typically contain an inactive area near the edges of the device. This scheme allows for dicing of the wafers (thin slices of semiconductor material) resulting in large device defect densities. Also, the existence of up to a 1mm wide inactive band leads to efficiency gaps when a larger surface is covered with many such devices. Researchers at UCSC in collaboration with the U.S. Naval Research Laboratory (NRL) have developed methods for fabricating resistive semiconductor sidewalls near the active area that allow deep depletion operation. These methods can be used to make compact, low-cost sensor devices without inactive periphery. Moreover, this robust and scalable method could be used for IC (integrated circuit) production, power electronics IC production, radiation detector (or sensor) production, imaging sensors, and solar cell production.    

This present invention describes the design of a miniature capacitive switch with a footprint less than 10 mm2 that can handle up to 100 W of radio frequency (RF) power. This invention also relates to methods of manufacturing these capacitive switch devices directly within or on any of the following: lead frames, substrates, microelectronic packages, printed circuit boards, flex circuits, and rigid-flex materials.

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In order to overcome fundamental energy efficiency limits of CMOS technology, micro-electro-mechanical (MEM) relay technologies are now being investigated for ultra-low-power digital integrated circuit (IC) applications. High relay endurance (exceeding 10^14 ON/OFF switching cycles) is required for relay-based ICs to be viable, and has been a major challenge due to stiction and wear. Researchers at UC Berkeley have developed an efficient way to reduce contacts aging, stiction, and oxidation. The researchers have shown that contacts can be made to be very reliable with very low resistance. To date, a contact resistance of 85.2 kohms has been measured at room temperature and suggests the possible use of these contacts for relay-based integrated circuits, which typically requires contact resistances less than 100 kohms. Further work will include coating optimization, surface roughness analysis, dynamic measurements for contact aging evaluation, thermal analysis, extraction of the effective contact area, and advanced current transport modeling.

The growing complexity of integrated circuit (IC) designs is increasing the need for multiple planarization steps in the IC manufacturing process. The primary method of achieving these planar surfaces is called Chemical Mechanical Planarization (CMP), and the pads that are used in conventional CMP are prone to inconsistent polishing leading to non-uniformity and imprecision in the IC wafers. These conventional CMP pads also require conditioning which can lead to pad contamination resulting in scratches and other defects on wafer surfaces. Preventing defects on wafers is critical as a single defect can ruin a $1 million wafer. Moreover, improving the CMP polishing rate can decrease the time and cost of this manufacturing process. To address these issues, researchers at UC Berkeley have developed a new CMP pad design that provides the maximum amount of polishing while minimizing pad degradation and in turn ensures efficient and consistent polishing performance. The Berkeley CMP pads enable efficient slurry delivery leading to faster rates of material removal. This pad design also doesn't require conditioning and thereby reduces the manufacturing complexity and the cost of manufacturing consumables. Additionally, the Berkeley pads can readily support MEMS sensors that can be used for end-point detection of the CMP process; and they are an enabling technology in the commercialization of NEMS because the Berkeley pads don't have the 10 nm minimum feature size limitation of conventional pads.

Aggressive scaling of semiconductor memory cells and the dramatic increase in the memory size array demand high density/low cost flash memory. Floating gate flash memory devices are the state-of-the-art in commercial nonvolatile memory, although they suffer from slow programming speed and show a degradation in performance after approximately 105 program/erase cycles. Also, achieving the benchmark 10-year retention time requires an operating voltage of >10V, which in turn requires peripheral supporting circuitry consuming a large portion of the memory chip area. Further, it is questionable whether conventional flash memory devices can be scaled below the 65 nm technology node. Researchers at the University of California, Berkeley have invented an improved flash memory device with program/erase speeds as fast as a nanosecond at an operating voltage as low as 2V in 0.13 micron technology. Research and modeling to date indicate that the improved device can meet or exceed the 10-year retention time standard, with no performance degradation through 109 program/erase cycles. The memory core density is comparable to state-of-the-art flash memory, and may be aggressively scaled for high density memory chips including solutions below 65 nm. Like conventional flash memory, Berkeley?s improved flash memory device is compatible with the current CMOS process flow.