This technology introduces a revolutionary receiver architecture capable of demodulating high-order QAM signals without the need for high-speed analog-to-digital converters (ADCs), significantly enhancing communication speed and efficiency.
The invention presents a novel receiver architecture designed for ultra-high-speed communications, employing a carrier synchronization loop and a high-speed pipelined structure. This architecture uniquely demodulates high-order QAM signals directly into raw bit-streams, bypassing the need for ADCs in the signal path and addressing the critical bottleneck in conventional receiver designs.
Country | Type | Number | Dated | Case |
Patent Cooperation Treaty | Published Application | WO 2024/020140 | 01/25/2024 | 2022-939 |
Additional Patent Pending