UCLA researchers in the Department of Electrical Engineering have developed a novel method of powering systems on silicon interconnect fabrics for integration of packageless processors.
Over the past two decades, silicon chips have decreased in size by 1000x, while packages on circuit boards have only shrunk by 4x. This will eventually limit scaling of integrated circuits and subsequent processor performance. A solution is the invention of platforms for packageless integration of heterogeneous dies, such as silicon interconnect fabric (Si-IF), exhibiting significant improvements in thermal and electrical properties. However, novel power distribution networks for Si-IF must be designed for successful further innovation in this field.
Professor Iyer and coworkers have developed a novel method of powering silicon interconnect fabric (Si-IF), a novel platform for heterogeneous systems integration. In this approach, a series of copper stubs are used to connect the back of the Si-IF to the socket. The front of the Si-IF is then powered using through wafer vias (TWVs), which penetrate the silicon substrate. This proposed network demonstrated a voltage drop of 298 µV (distributed voltage of 12V), can distribute multiple voltage domains, and only dissipated 248 mW of power.
Power distribution network for high power systems integrated on silicon interconnect fabric
A silicon interconnect fabric sample with 63,600 mm2 effective area can be powered using this power distribution network. Through wafer vias and copper stub parameters were optimized, resulting in a power distribution network with a voltage drop of 298 µV (distributed voltage of 12V) that supports distribution of multiple voltage domains of 12V and 3.3V, and only dissipated 248 mV of power.
|Patent Cooperation Treaty||Reference for National Filings||2019089935||05/09/2019||2018-337|
silicon interconnect fabric, power distribution network, packageless processors,