Researchers at the University of California, Davis have developed a phase noise filter (PNF) circuit with wide bandwidth and high sensitivity.
Phase noise limits the performance of many microsystems. Phase noise within clocks or local oscillators interferes with the bit-error-rate of digital systems and the resolution of analog-digital/digital-analog converters. It also interferes with the signal-to-noise ratio of radio-frequency systems. This interference compromises between phase noise performance and wide bandwidth and flexibility.
Researchers at the University of California, Davis have developed a passive delay line frequency discriminator and delay line frequency discriminator and phase detector/charge pump-based phase noise filter (PNF) circuit that achieves wide bandwidth and high sensitivity. The PNF circuit has reliable integration capabilities at 10 GHz due to its insensitivity to amplitude and coupling noise. The circuit also offers a high potential solution for ultra-sensitive, high-reliability, and on-chip phase noise measurements. The phase noise filter has already been used in a proof-of-concept demonstration to suppress clock phase noise >15 dB.
|United States Of America||Issued Patent||10,075,145||09/11/2018||2014-999|
|United States Of America||Issued Patent||9,667,219||05/30/2017||2014-999|