Researchers at the University of California, Davis have developed a high-efficiency broadband doubler.
Complimentary metal-oxide-semiconductor (CMOS) technology has been extended to transceive circuits in the millimeter, high frequency range. High frequency signals offer larger bandwidth availability and require smaller dimensions for gain relative to antenna size compared to low frequency signals. In typical cases, a local oscillator is required to generate the signals modulated by CMOS. These local oscillators, however, have difficulty in generating stable, low phase noise and require a lot of power due to inefficiency at high operating frequencies. Thus, there is a need for a high efficiency broadband multiplier with high efficiency and output power to address the performance of local oscillators at high frequencies.
Researchers at the University of California, Davis have developed a push-push frequency doubler which adopts transformer based input balun with a newly invented central compensation capacitor for matching and balanced signal generation. The invention has a compact size and by choosing proper value of the compensation capacitor, the balun can achieve good balanced performance. The doubler is fabricated in a 65 nm chip area and consumes 9–14 mW power. It demonstrates a peak conversion gain of 2.5-dB and peak efficiency of 9.7% with a saturated output power of 2.5-dBm at 74 GHz. The doubler exhibits a 3-dB CG bandwidth of 28 GHz from 62 to 90 GHz and the fundamental rejection is larger than 20-dB.
|United States Of America||Issued Patent||10,355,678||07/16/2019||2015-764|