Scalable Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation

Researchers in the UCLA Department of Electrical Engineering have developed a scalable and parameterized VLSI architecture for compressive sensing (CS) sparse approximation, allowing for energy-efficient, cost-effective, and real-time compressive-sampled data processing in wireless/mobile healthcare applications.

Wireless healthcare technology makes medical resources more accessible while also lowering cost, increasing the engagement between patients and doctors and promoting connectivity for improved therapy. One of the key challenges in wireless healthcare is the lack of efficient sensing technology, as the continuous monitoring on health status will inevitably generate large amount of data for transmission/storage/analysis. Today’s digital electronics industry relies on the Nyquist sampling theorem, which requires doubling the size (sample rate) of the signal representation to avoid information loss. However, most natural signals result in a large redundancy in Nyquist-sampled data, necessitating data compression prior to storage or transmission. Recent advances in compressive sensing theory offer an alternative data acquisition framework. However, applying the compressive sensing technology in real-time systems involve solving an optimization problem, which requires iterative-searching algorithms that have high computational complexity and data dependency. Existing software solutions are neither energy-efficient nor cost-effective for the real-time processing of compressively-sampled data, especially when the processing is to be performed on such energy-limited devices.

The Markovic Lab in the UCLA Department of Electrical Engineering has created a parameterized and scalable VLSI architecture that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs), or system-on-chip (SoC) designs to perform hardware-accelerated sparse approximation—the core processing block for performing the reconstruction or classification of compressive-sampled data. The architecture core supports a floating-point data format with a number of design parameters, providing the necessary flexibility for application-specific customization. By compressing sensor data by a factor of 3, that much power can be saved, extending the battery life of the sensors and offering a significant advantage for wireless and mobile healthcare applications.

Wireless/mobile healthcare:

The system has been evaluated on a 28nm Xilinx Kintex-7 FPGA to show the same level of accuracy as the double-precision C program running on an Intel Core i7-4700MQ mobile processor, while providing 47-147 times speed-up and 3-4 orders of magnitude better energy efficiency. A 40nm silicon prototype has also been developed, which can provide real-time sparse signal reconstruction in less than 20mW, as compared to 20W on existing CPU and GPU platforms.