Distributed Energy Conserving LC Resonant Clock Trees

Background

Clock networks in high-performance designs are extremely power hungry. One method to reduce high power consumption is to use distributed LC tanks. By shifting between electrical and magnetic forms at the resonant frequency, these LC tanks conserve energy. However, no physical algorithms for the synthesis of resonant trees have been proposed before now. UC Santa Cruz is the first to present an algorithm to synthesize resonant region clock trees in ASIC’s.  

Description

UC Santa Cruz researchers have developed the first algorithm to achieve significantly reduced power in integrated circuits. UCSC’s highly effective algorithm synthesizes resonant regional clock trees using distributed LC tanks. This resonant technique can be used in both ASIC’s and custom microprocessors, and the algorithm attained a record 41.7% power reduction and an 8.4ps skew reduction. Despite increasing inductor and capacitor area, the algorithm reduces the total buffer area required. Thus, the UCSC algorithm has potential to make clock networks low cost and energy conserving.  

Applications

• Integrated circuits

Advantages

• Over 40% power reduction with a modest 8.4ps skew reduction
• Reduces the total buffer area required
• Low cost 

Patent Status