DESIGN WORKFLOW IMPROVEMENTS USING STRUCTURAL MATCHING FOR FAST RE-SYNTHESIS OF ELECTRONIC CIRCUITS

Tech ID: 32773 / UC Case 2018-689-0

Background

Electronic circuits are growing in complexity every year. Existing workflows that optimize the design and placement of circuit components are laborious and time-consuming though. Incremental design changes that target device optimization can take many hours to render. Streamlined design workflows that are both fast and able to optimize performance are needed to keep pace with these device improvements. A UC Santa Cruz researcher has developed a new technique, SMatch, to shorten design workflow times with minimal QoR impact. 

Technology Description

UC Santa Cruz researchers have developed SMatch, a method that uses an incremental FPGA flow to skip placement and routing for matching blocks. This method significantly shortens runtime while maintaining QoR by reducing the overall number of LUTs needed to be placed and routed. SMatch is generally 20x faster than other incremental commercial FPGA flows and is able to deliver many of the changes set by the Anubis benchmark suite in under 30s.

SMatch

Applications

  • Electronic design automation workflow for commercial use


Advantages

  • 16 to 20x faster synthesis, placement, and routing than current state-of-the-art flow, LiveSynth
  • Comparable QoR


Intellectual Property Information

Patent Pending

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Inventors

  • Possignolo, Rafael
  • Renau, Jose

Other Information

Keywords

Electronic device automation, EDA, Design workflow, Synthesis, Chip design, Structural Netlist, FPGA - Field Programmable Gate Array, Hardware Description Language, Lookup Table

Categorized As

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