Low-noise Low-power ADC for Direct Biopotential Recording in Neuroscience Applications

Background

High-density multi-channel neural recording is critical to driving advances in neuroscience and neuroengineering through increasing the spatial resolution and dynamic range of brain-machine interfaces.  Neural signal acquisition ICs have conventionally been designed composed of two distinct functional blocks per recording channel: a low-noise amplifier front-end (AFE), and an analog-digital converter (ADC).  Hybrid architectures utilizing oversampling ADCs with digital feedback have seen recent adoption due to their increased power and area efficiency. However, input dynamic range (DR) is still relatively limited due to aggressive supply voltage scaling and/or capacitive sampling noise.

Technology Description

Researchers at UC San Diego have an invention that represents the first neural recording ADC chip with 92dB dynamic range and 0.99µVrms of noise at 0.8µW power consumption per channel over 500Hz signal bandwidth, owing to:

• a predictive digital autoranging (PDA) scheme in a hybrid analog-digital second-order oversampling ADC architecture; and

• no specific sampling process through capacitors, avoiding kT/C noise altogether.

Applications

By digitally predicting the analog input at 12-bit resolution from a single-bit quantization of the continuously integrated residue at an effective 32 oversampling ratio (OSR), the PDA handles a ±130mV electrode differential offset (EDO) and recovers from >200mVpp transient artifacts within <1ms. Furthermore, using digital circuits for integration ensures the architecture benefits from process scaling and the resulting compactness makes it suitable for incorporation in high-density recording arrays.

State Of Development

A working prototype has been developed in a 65 nm CMOS process.

Intellectual Property Info

Patent pending under US Utility application #16/271,739

Related Materials

• C. Kim ; S. Joshi ; H. Courellis ; J. Wang ; C. Miller ; G. Cauwenberghs. A 92dB dynamic range sub-µVrms-noise 0.8µW/ch neural-recording ADC array with predictive digital autoranging. Published in: 2018 IEEE International Solid - State Circuits Conference - (ISSCC). DOI: 10.1109/ISSCC.2018.831038812 - 03/12/2018

Patent Status