Clock Power Reduction Utilizing Adiabatic Charging Method Via a Switched-Capacitor Circuit

Tech ID: 28834 / UC Case 2017-199-0


Normally, charging a capacitive load from a voltage source invokes a ½ CV2 energy penalty. The concept of adiabatic charging, where the capacitor is charged more slowly than nominally afforded by the natural RC time constant of the charging circuit in the pursuit of reducing energy dissipation to below ½ CV2, has been around for decades. However, there has not been any solution to enabling this slow charging phenomenon in a practical, low-overhead embodiment. For example, prior work used separate DC-DC converters to provide multiple voltage levels, or used resonant inductors, both of which invoke significant area overhead.

Technology Description

Researchers at UC San Diego invented a way to efficiently charges capacitive loads (e.g., clock trees, I/O pads, bio-electronic stimulators, etc.) via a step-wise adiabatic process. The present invention provides multiple levels in a small, efficient structure via a switched-capacitor approach to enable adiabatic charging for the first time in a practical solution. The technology was demonstrated in a clocking application.


This invention has promising applications for any company doing digital design. Further applications include use in I/O drivers and neural stimulation.


Efficient charging of capacitive loads in a minimized form factor.

State Of Development

Complete, working prototype.

Intellectual Property Info

A provisional patent has been submitted, the technology is available for licensing.

Related Materials

  • Loai G. Salem, Patrick P. Mercier. A 0.4-to-1V 1MHz-to-2GHz Switched-Capacitor Adiabatic Clock Driver Achieving 55.6% Clock Power Reduction ISSCC pp 442-444 2017 Feb 8,2017 - 02/08/2017

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 10,348,300 07/09/2019 2017-199


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Other Information


adiabatic charging, capacitive loads, clock trees, bio-electric stimulators, digital design

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