A Self-Organized Critical CMOS Circuit for Computation and Information Processing

Summary

UCLA researchers in the Department of Electrical Engineering have developed a novel system architecture for solving optimization problems faster using chaos or self-organized criticality to generate a matrix of bits for computation.

Background

Conventional computers are efficient in solving sequential arithmetic problems but they are inefficient in solving problems with many interacting variables. Such problems usually do not have exact analytical solutions and are often deemed non-deterministic polynomial-time hard (NP-hard) for conventional computers. Annealing approaches have been proposed but generally suffer from slow processes and lack the means for reliably reading out solutions. Meanwhile, demand is increasing for computational systems that can solve such complicated problems, as they arise in the form of image recognition, modeling physical systems and optimizing large systems.

Innovation

The proposed system architecture leverages recent breakthroughs in the understanding of the self-organized criticality phase in complex dynamics systems to solve optimization problems much faster. The system converges to a global minimum much faster than conventional simulated and chaotic annealing approaches implemented in software.

Applications

Faster optimization problem solver in any computer.

Advantages

• Outperforms conventional simulated or chaotic annealing implemented in software
• Ability to provide intermediate candidate solutions, which chaotic annealers cannot do

State Of Development

The system has been validated in circuit simulations. Testing of a successfully fabricated device is underway.

Patent Status