|United States Of America||Issued Patent||10,224,875||03/05/2019||2014-090|
Frequency dividers have become essential components of phase-lock loops and frequency synthesizers that are used in a variety of applications from instrumentation to wireless handsets. In a typical frequency synthesizer application, frequency dividers often limit the achievable phase noise performance and contribute a large or even majority portion of the total power consumption. Common digital dividers offer good noise performance, but at the cost of power far in excess of that permissible for mobile applications and with poor scaling as frequency is increased. To alleviate this, injection-locked oscillator dividers have emerged as low power options at high frequencies, but they have performance limitations due to the active transistors used to sustain oscillation.
To overcome these limitations, researchers at UC Berkeley have developed a new design for frequency dividers. While performing a frequency divide-by-two function, a version of this on-chip MEMS-based frequency divider reduced phase noise by 6 dB at close-to-carrier frequencies and 23 dB far-from-carrier. Unlike conventional frequency dividers, this Berkeley design dispenses with active devices and their associated noise, and operates with close to zero power consumption, limited in principle only by the power required to overcome MEMS resonator loss, estimated at 100 nW. With an output voltage swing of 450 mVpp generated from only 445 mVPP of input swing on a version of this MEMS divider, cascaded chains of fully passive dividers are possible, as needed for use in real-world phase-lock loops and frequency dividers.