Organic electronic devices such as organic light emitting diode (OLED) and organic photovoltaics (OPV) must be protected from water and moisture, which can react with both organic and inorganic active layers and degrade performance. Thin film inorganic layers can be deposited by sputtering, but they tend to produce a large number of defects. The standard CVD requires high temperature and so is incompatible with OLED.  Plasma enhanced CVD (PECVD) reduces processing temperature but suffers from heavy ion bombardment, and plasma-induced vacuum ultraviolet (VUV) irradiation onto the sample. To address these challenges, investigators at University of California at Berkeley have developed  a laser-assisted chemical vapor deposition (LACVD) system for providing thin film oxide & nitride encapsulation of organic electronic devices.  This LACVD encapsulation system allows, for the first time, encapsulation of organic optoelectronic devices, such as organic light emitting diodes (OLED) and organic photovoltaics (OPV).  Low substrate temperature operation by LACVD permits deposition on temperature-sensitive materials such as polyacrylate layer.  (more...)

A novel method of altering the effective contact resistance between two semiconductor layers.  (more...)

A novel invention to enable the fabrication of (In,Ga,Al)N optoelectronic devices with thick active layers containing a high concentration of indium (In).  (more...)

A novel method to fabricate high-performance, low voltage GaN-Based green LEDs and laser diodes (LDs).  (more...)

University researchers have developed a miniature relay switch, with an overall volume of less than 100 mm3 that can handle up to 40 W of DC or 60 Hz line power. This invention also relates to methods of manufacturing these relay devices directly within or on any of the following using standard electronic manufacturing techniques: lead frames, substrates, microelectronic packages, printed circuit boards, flex circuits, and rigid-flex materials. (more...)

By exploiting non-reciprocal magneto-optic micro-ring resonators, a single hybrid III-V semiconductor optical amplifier can be effectively integrated to provide crosstalk-free bidirectional interleaved WDM communication for intracard active optical interconnects.               (more...)

Media storage has advanced substantially, and is in ubiquitous use in industry and consumer products.  A major challenge for media storage is that electromagnetic radiation or DC magnetic fields can damage or destroy that memory.  By example, in consumer banking, each transaction lost due to magnetic media failure represents a substantial reduction of profit. To address this challenge, investigators at University of California have developed an electromagnetically robust memory storage.  This innovative, single material magnetoresistive universal memory is  insensitive to external electromagnetic perturbation.  The electromagnetism proof memory breakthrough comes from the writing procedures requiring two excitations. Because these memory writing approaches must be applied simultaneously, it cannot be damaged by uncoordinated occurrences near the writing embodiment. The information is read by the most simple electric measurement, namely 'ohmic resistance', thus the technical realization of embodiments for storing the data, editing the data and reading is enormously simple.  The electromagnetism proof memory can be used for either low-density or high-density data storage media such as credit cards, identification cards, access cards, or maps base for navigation. (more...)

Many crystalline materials can be grown on foreign substrates; but for their intended applications, materials often need to be either free from the substrate or transferred to a different substrate. One such example is where there is a need to obtain a device structure where a direct bandgap semiconductor (e.g., GaAs) is combined on silicon, or to place an optically active material on an optically transparent or a highly thermally conductive substrate. (more...)

First time demonstration of enhanced formation of polymers on nanostructures under X-ray irradiation. (more...)

A novel approach for producing a GaN-based semi-polar-oriented light emitting diode (LED) that contains a thin p-type GaN layer and no AlGaN electron-blocking layer (EBL). (more...)

A polarized LED and a method of fabricating and packaging the device. (more...)

A bipolar transistor through a mechanism based on spin polarization. (more...)

New LED structures that provide increased light extraction efficiency while retaining a planar structure. (more...)

A phosphor-free white light source, where an indium-containing light-emitting layer, as well as subsequent device layers, is deposited on a textured surface. (more...)

In many thermoelectric applications there is benefit in heterogeneously combining an active thermoelectric conversion material with a good thermal and electrical insulator including air or vacuum as possible candidates. In such configurations it is possible to decrease the cost of device fabrication due to decreased material costs. It is also possible to tune the total thermal resistance of a system by tuning the fraction of active to insulating (Atol) region which can in turn be used to select the operating temperature if the heat flux is known as is often the case. The ability to tune the temperature by controlling the fraction of Atol will enable designers to create devices which operate at optimal temperature ranges for decreased cost.   Design challenges include overcoming electrical resistance resulting from strategic reduction in materials and the increased parasitic electrical and thermal resistances due to the avoidance of the heat-spreader with expected resistance to conduction. (more...)

Most of the resources in modern processors are specifically built to support memory operations. To support fast and efficient loads and stores, processors implement multiple cache levels, cache coherence, non-blocking caches, Translation Lookaside Buffers (TLB), Load-store queues, and store set predictors. Most of these resources are on the critical path of load operations. A slow load operation significantly affects the overall system performance. This means that the supporting structures must cycle in just a few cycles. Among other parameter, architects trade between memory access time and area, power and/or complexity. Larger structures have longer access times, but small structures have more structural hazards (load-store queues, miss status handing register) or the miss rates (caches, TLB’s). Additionally, fast transistors tend to consume more dynamic and static energy.  Optimizing memory operations is key for processors and multicore systems. To provide fast memory accesses, processors implement a fast but complicated and inefficient memory subsystem.  (more...)

Clock networks in high-performance designs are extremely power hungry. Currently there is not a methodology to create resonant clock meshes that resonate at multiple frequencies. Dynamic frequency scaling is common technique to save power in both the clock network and in data-path logic on computer chips. While prior resonant clock networks can save power by recycling energy in the clock network, they do not save any power in the data-path logic. Prior resonant clocks only work at a single resonant frequency (more...)

The primary application for gyroscopes is in navigation.  While the currently available gyroscopes have important applications, these are limited due to large size, and sensitivity to temperature.To meet these challenges, investigators at University of California at Berkeley have developed a miniature diamond gyroscope, based on nitrogen vacancy centers in diamonds. This miniature diamond gyroscope extend the capabilities of existing technology by enabling gyroscopes of very small sizes.  The miniature diamond gyroscope provides new technique for sensing rotations based on the negatively-charged nitrogen-vacancy NV center in diamond.  The key advantages of this technology is that it is all-solid-state, operates over a wide range of temperatures.  The active part of the sensor is very small, on the scale of 1 cubic millimeter.  The sensitivity under optimal conditions is comparable to or better than other large scale gyroscope technologies. Publication- http://arxiv.org/abs/1205.0093, (more...)

Light-pulse atom interferometers (LALIs) are useful as inertial sensors, measuring acceleration and rotation. In addition to being extremely sensitive, LAIs show a highly accurate scale factor and stable baseline even without calibration, unlike classical sensors such as laser gyroscopes. Rotation sensing however, does not yet benefit fully from this stability.  In existing sensors, one of these dimensions for the enclosed area A is determined by the atoms’ initial velocity, a quantity known to relatively low precision. Moreover, all LAIs, including “compact” versions for inertial navigation, use beam splitters based on Raman transitions (which limit their sensitivity and introduces systematic effects), atomic fountains (which are ~1-m tall and must be carefully aligned with respect to the vertical), and free-beam optics (which limit available laser intensity and wavefront purity). To address these challenges, investigators at University of California at Berkeley have developed a cavity-based atom interferometer which overcomes these limitations.  This atom interferometer is provided a 40 cm optical cavity to enhance the available laser power, minimize wavefront distortions, and control other systematic effects symptomatic to atomic fountains.  This innovated system allows the production of LAI inertial sensors that simultaneously measures linear accelerations and rotations. The cavity-based interferometer offers the full performance of a large-scale atomic fountain within a small volume.  The cavity-based interferometer will surpass the baseline stability of current rotation sensors.  It will allow spatial separations between atomic trajectories comparable to larger scale fountains within a more compact device. (more...)

This present invention describes the design of a micro-structured plate for controlling the capacitance of a mechanical capacitor. The capacitance value can be changed by simply changing the number and size of the micro-structured plates. (more...)

Current approaches to print micro and nanoparticles are promising, but have serious limitations to commercial applications. These methods require high power consumption and have complicated and costly set-up. These systems are low-throughput, have limited pattern size and resolution-tunability, and difficult alignment. In response to these challenges, investigators at University of California at Berkeley have developed zero-power nanoparticle printing system. This system uses gravity and surface tension to generate and print picoliter-scale droplets for high-throughput, size-tunable printing of micro, nanoparticle assemblies. High-throughput, picoliter-scale droplets are printed by a single step, contact-transferring of the droplets through microporous nanomembrane of a printing head. Rapid evaporative self-assembly of the particles on a hydrophobic surface leads to printing a large array of various microparticles and nanoparticles assemblies of tunable sizes and resolutions. With this technology, continuous printing of single type particles and multiplex printing of various types of particles with accurate alignment are successfully performed. As a demonstration of this innovation, the investigators have produced size-tunable, uniform large arrays of gold nanoparticle assemblies for Surface Enhanced Raman Spectroscopy (SERS) are created. Strong and uniform (<10% variation) SERS signals were obtained and the signal is tunable by controlling the pattern sizes. Also, the superb uniformity of the printed patterns is demonstrated in a quantitative manner. This technology offers a straightforward, efficient methodology to manufacture nanophotonic and nanoelectrical devices in a controllable way with low power and material consumption. (more...)

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The NAND flash memory has a simple cell structure allowing for higher density and more memory capacity. Further, it is ideal for mobile devices because flash memory is highly durable and able to withstand mechanic shock, high pressure, temperature, immersion in water, etc. Solid state drives, based on NAND flash memory, are lower in cost compare to DRAM and are able to retain data without a constant power supply. However, the cost per gigabyte compared to the conventional hard drive is still considerably higher. Flash memory technology will need to evolve in order to continue to scale and to have a stronger presence in the marketplace (more...)

A novel method for growing group-III nitride crystals for use as seeds for ammonothermal growth of group-III nitride crystals. (more...)

Photolithography, an essential process in the fabrication of integrated circuits, has undergone continuous advancements that allow patterning of nanometer sized features. For example, features as small as 50 nm can be made by using excimer lasers with wavelengths of 248 nm and 193 nm (i.e., deep ultraviolet light). However, it is not always feasible for scientists to use the short wavelength lasers because they are expensive. A method that allows for high resolution photolithography without large capital expenses will be very useful. Researchers at the University of California, Irvine have developed a photolithography method that allows for high resolution patterning. By using this method, one can get a 20-fold improvement in the limit of resolution in comparison to the inherent resolution of “top-down” processing. In addition, the method is easy to use, inexpensive, and does not require sophisticated instrumentation. (more...)

Nanowire-based material systems offer a variety of advantages over traditional thin film systems, and as such device applications are being sought extensively. The great majority of existing device applications are based on single nanowires or nanowires which operate independently of each other. UCSC’s unique material system based on randomly oriented and intersecting semiconductor nanowires grown on amorphous substrates leads to three-dimensional nanowire networks which allow long-range carrier transport from one nanowire to another. The nanowire network enables nanowire-based devices to be designed with added functionality including electrical and thermal transport in directions nominally perpendicular to the surface normal of a substrate on which the nanowire network is formed. By utilizing nanowire networks that allow electrons and holes to travel over distance much longer than the length of a single nanowire, it is possible to envision entirely new device architectures based on novel operational physics. (more...)

A novel VCSEL cluster for use in high power applications. (more...)

A novel method for creating a VCSEL structure that confines current diameter to less than that of the transverse optical mode, while maintaining a high degree of planarity in its layers. (more...)

A novel method for making a metal layer semiconductor laser with large bandwidth and the capability for high power output. (more...)

A technique for forming conductive feedthroughs in a silicon wafer, such that a bonding site on the front of the wafer also has a corresponding bonding site or pad on the backside. (more...)

Conventional approach to controlling and modulating carrier transport in transistor is by utilizing external electric field. In a typical setting, metal or heavily doped silicon gate is separated by dielectric materials from the active region of semiconductor, forming a metal-insulator semiconductor structure. However, such approach requires physical metal interconnections to the device for electrical modulation, which are constructed up to at least 10 interconnection layers in the state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology. As the technology advances, these interconnections become more and more complicated, and significantly burden the operation of the transistor due to increased parasitic components of the circuit (i.e. parasitic resistance/capacitance). In order to address such challenges, researchers at the University of California, Berkeley have developed optical interface capable of wireless modulation of electrical current, instead of complicated physical metal interconnects. In particular, they have developed a interface to demonstrate the free-space optical modulation of current. The new capability of optical modulation allows a new class of transistor optical transistor - with unprecedented performance and tunability. Furthermore, The two critical applications of the new transistor - multi functional logic gates, and ultra-sensitive electrical detection of biomolecules – enable completely new possibilities for multifunctional electronics and ultra-sensitive detection of chemical and bio- molecules. The uniqueness of wavelength-specific modulation of nanophotonic transistors lead to the creation of multi-functional nanophotonic logic gates and circuits where different component generate multiple functionalities in a same circuit layout. In addition, local field enhancement provides a unique opportunity to substantially improve sensitivity of field-effect transistor (FET) based biosensors. (more...)

A new circuit and control method consisting of new bootstrap gate drivers with the redundant switching states for the multilevel converters. Based on the new bootstrap capacitor charging method and the use of the redundant switching states, the proposed bootstrap gate drivers can achieve stable bootstrap capacitor voltages with minimum capacitance and wide operation range. (more...)

A laser diode that presents improved structural, electrical and optical properties of long wavelength laser diodes, especially in the blue-green spectral range. (more...)

An ammonothermal growth method for high-quality group III-nitride bulk crystals at commercially practical growth rates. (more...)

A novel method for defect reduction via lateral growth of semipolar nitrides (more...)

Sidewall lateral epitaxial overgrowth (SLEO) of non-polar a-plane and m-plane GaN that results in several device improvements such as longer lifetimes, less leakage current, more efficient doping and higher output efficiency. (more...)

A technique for the growth of planar films of semi-polar nitrides, in which a large area of (Al, In, Ga)N is grown parallel to the substrate surface. (more...)

A novel method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. (more...)

A light emitting diode (LED) that combines a high-efficiency LED chip with shaped phosphor layers to increase the total luminous efficacy of the device.(UC Case 2007-272 and 2007-273) (more...)

An LED design that can emit white, single, or multi-color light. (more...)

A device with increased efficiency by combining shaped high refractive index elements with an (Al, Ga, In)N LED and shaped optical elements. (more...)

A method for enhancing growth of semipolar (Al,In,Ga,B)N films for high-performance nitride-based optoelectronics and semiconductor devices. (more...)

Highly-efficient cleaved facet edge-emitting laser diodes grown on semipolar gallium nitride substrates. (more...)

Flash, SSD, and Storage Class (SCM) technologies stand to replace magnetic disk technology as the mainstay for high end applications. However, magnetic disk technology will continue to play an important role in large storage systems, due to the sheer amount of data to be stored, the attractive cost-to-capacity ratios of disks, and the high steaming throughput. Although, disk drives offer decent performance (especially when accessing large blocks of data) and very low cost per GB, they are mechanic-electrical devices with moving parts, which subjects them to relatively high annual failure rates. This failure rate contributes to a heightened sensitivity in assessing liability associated with the loss of data; resulting in some companies using triplication of disk storage devices to protect data (e.g., internet searches). While replication offers operational advantages, the storage overhead and its associated costs in hardware, maintenance, and energy is too large.  (more...)

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The exponential decrease in transistor size has been the driving force behind the increasing performance and rapid growth of information technology; however, continued scaling through the current standard manufacturing practices employed by the semiconductor industry will result in reduced performance. Although, one method to improve performance without replacing silicon with expensive materials, is to enhance carrier mobility by applying strain to silicon; the current strain techniques suffer from dislocation, resulting in non-uniform strain, non-flat surface morphology, and strain relaxation, which in turn reduce the mobility enhancement. (more...)

Due to their design versatility and lower cost, FPGA systems are increasingly favored in comparison to their ASIC counterpart. However, because FPGA is more vulnerable to soft errors it is essential to improve its fault tolerance. While many techniques have been proposed, the majority do not preserve the topology of the logic network and therefore require a new round of physical design. This is not only costly and time-consuming, but it also delays convergence between logic and physical syntheses. (more...)

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A novel method for fabricating potential barriers in N-face nitride-based electronics, applicable in high-performance transistors and other semiconductor devices. (more...)

This invention describes an enhancement of a voltage-controlled oscillator (VCO) realized using a CMOS fabrication process. The purpose of this invention is to reduce the oscillator’s sensitivity to perturbations in the supply voltage. Such perturbations can cause excess jitter in the VCO output, which increase the bit error-rate of the communication system in which it is implemented. (more...)

Fabrication of silicon-on-insulator (SOI) wafers with the top silicon layer less than 100 nm thick, as required by the International Technology Roadmap for Semiconductors (ITRS), has approached the process limits of conventional ion-implantation-based techniques. In particular, fluctuation in thickness becomes as high as several tens of a percent when forming a thin film of sub-micron thickness. The difficulty of forming a thin film with high crystalline quality becomes more severe with increasing wafer diameters. This invention can make significant improvements in the control of the thickness, the layer quality, and the surface smoothness of the transferred mono-crystalline thin layer. (more...)

A new avalanche photodiode that is low noise and provides a highly stable gain at small bias voltages. (more...)

A broadband absorptive multiplier as used in CMOS technologies is presented here and relates to microwave multipliers or mixers in general and in particular to absorptive switch networks for use in integrated wireless systems with very high bandwidth. (more...)

In electron beam lithography (EBL), after developing, the cross section of the resist has a parabolic undercut with a linewidth determined by the exposure in the top resist layer resulting in a typical linewidth of 100nm. (more...)

Several industries, such as the semiconductor and packaging industries, commonly uses plasma generators in equipment designed for fabricating circuits with demanding precision requirements. Helicon sources have many industrial uses because of their superior efficiency in generating dense plasmas. However, these sources require a DC magnetic field, which increases the cost and complexity compared with other RF plasma generators. A possible solution would be to replace the electromagnets with permanent magnets (PMs), which would reduce cost and complexity issues. For PMs to be a viable replacement, however, a device must be designed to counteract the PMs tendency to direct plasma into the walls rather than inject it into the process chamber because of PM field lines. (more...)

Modern VLSI designs see a large impact from process variation as devices scale down to nanometer technologies. Not surprisingly, process variations in nanometer technologies are becoming important considerations for the design of cutting-edge FPGAs with millions of logic gates. As device features scale down, FPGA complexity per area increases while process variations induce large differences in performance amongst chips. As a result, it is becoming increasingly difficult to design FPGAs in a timely fashion or with reasonable yield. However, using trace-based timing and leakage modeling with process variations, these challenges can be overcome. (more...)

Silicon on insulator (SOI) made of an insulating silicon dioxide layer in between two single-crystal silicon layers is an attractive way to improve the efficiency of semiconductor devices such as a transistor or MOSFET. MOSFETs fabricated on a SOI substrate can be classified as fully depleted SOI having a relatively thin SOI layer or partially depleted SOI having a relatively thick SOI layer. A thinner layer can suppress leakage current between the source and drain, but is characterized by a higher parasitic resistance. Thus, the fully depleted SOI is advantageous for logic circuits but not for high-power circuit configurations and a partially depleted SOI is suitable for high-power circuit configurations but now for a logic circuit. The trend in the semi-conductor industry is towards higher packing density and multi-functionality of semi-conductor devices, creating a demand for mixed loading circuits, where a hybrid substrate having a SOI layer with partially different thicknesses can support different types of devices on a single chip. (more...)

Field effect transistors (FETs) provide a fundamental building block for electronic devices. Unlike conventional FETs, spin FETs are based on the manipulation of electronic spin states of electrical carriers. Spin FETs require an injector to introduce spin-polarized electrical carriers into the channel region. Diffusion-based current injection and tunnel injection have been used to inject charge carriers. However, diffusion-based current injection suffers from the electrical conductivity mismatch between ferromagnetic materials and semiconductors, prohibiting efficient spin injection. Tunnel injection suffers from high contact resistance which is detrimental to FET operations. (more...)

Ion beams for manufacturing and analytical applications (e.g.; ion beam milling, focused ion beam micromachining, and 3-D profiling of organic samples via secondary ion mass spectrometry) (more...)

This innovation is a Bragg-grating scheme developed on a silicon-on-insulator platform. It serves as a building block for optical components, such as filters, modulators, and resonators. This device consists of a silicon waveguide sandwiched between two rows of periodic silicon cylinders, set a fixed distance away from the waveguide. The coupling strength and dynamic range is easily varied by increasing or decreasing the separation distance between the periodic cylinders and the waveguide, giving excellent control of the coupling within the Bragg-grating and enabling filters of narrow to wide bandwidths. This approach is believed to be the first wherein the coupling strength in a Bragg-grating can be well controlled and predictably yield narrow bandwidth filters. (more...)

The subject invention employs two methods for layout decomposition for double patterning lithography (DPL) based on integer linear programming (ILP) formulations. In an exemplary embodiment of the invention, a pre-processing step fractures polygonal layout features into rectangles according to vertex coordinates of neighboring features. The fractured rectangular features are further split by a node-splitting process that resolves coloring conflicts and enlarges the solution space for DPL coloring. Then the coloring of the rectangles is optimized with a process-aware cost function that avoids small jogging line-ends and maximizes overlap at dividing points of polygons. The cost function may also be revised to make preferential splits at landing pads, junctions, and long runs. A layout partitioning heuristic helps achieve scalability for large layouts. There are two different layout decomposition approaches possible in the invention. The first approach (referred to as Conflict Cycle Detection, or CCD) performs conflict cycle detection to find and report coloring conflicts (i.e., design changes such as layout modifications are needed) then finds the coloring solution on the remaining features using an ILP formulation. The second approach (referred to as Pure ILP or PILP) directly computes the coloring solution on the rectangles after polygon splitting, along with the minimum number of necessary layout modifications, using a more sophisticated ILP formulation. An exemplary objective for the DPL layout decomposition methods is to optimize a weighted combination including number of design changes, number of line-ends, number of design rule violations, and the overlap lengths between touching features with different colors. Normal.dotm 0 0 1 252 1439 UCSD TechTIPS 11 2 1767 12.0 0 false 18 pt 18 pt 0 0 false false false /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:12.0pt; font-family:"Times New Roman"; mso-ascii-font-family:Cambria; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Cambria; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} (more...)

A new method using low temperature bonding to fabricate optoelectronic and electronic devices. (more...)

A method of fabricating solid state lasers with embedded structures for improved performance via patterning. (more...)

In order to overcome fundamental energy efficiency limits of CMOS technology, micro-electro-mechanical (MEM) relay technologies are now being investigated for ultra-low-power digital integrated circuit (IC) applications. High relay endurance (exceeding 10^14 ON/OFF switching cycles) is required for relay-based ICs to be viable, and has been a major challenge due to stiction and wear. Researchers at UC Berkeley have developed an efficient way to reduce contacts aging, stiction, and oxidation. The researchers have shown that contacts can be made to be very reliable with very low resistance. To date, a contact resistance of 85.2 kohms has been measured at room temperature and suggests the possible use of these contacts for relay-based integrated circuits, which typically requires contact resistances less than 100 kohms. Further work will include coating optimization, surface roughness analysis, dynamic measurements for contact aging evaluation, thermal analysis, extraction of the effective contact area, and advanced current transport modeling. (more...)

Recent developments in semiconductor manufacturing technology have resulted in unprecedented density of transistor elements per silicon area. This new technology facilitates a dramatic increase in circuit complexity of the modern computer and communication hardware. With transistors dimensions as low as 90nm, operation frequencies in the 5GHz range are possible and will surely be surpassed by the next generation of 60 nm devices. Increased switching frequency inevitably causes higher power dissipation and results in higher overall current consumption. Lower, junction breakdown voltages of only 1.2-1.5V are expected to become even lower in the future, thus posing a limitation on operating voltage level. According to Intel's Roadmap 2005, the next generation of processors will operate at 0.9V DC voltage, with current consumption of up to 120A. Systems current slew rate of 140A/uSec is expected when the processors come out of the power saving mode and vice versa when entering the sleep mode. (more...)

Transmit power consumption often governs the ultimate battery lifetime of portable wireless communications devices, and therefore transmit power amplifiers used in these devises are important to their commercial success. The efficiencies of these power amplifiers are set by the capabilities of the semiconductor transistor devices that drive them. The most efficient power amplifier configurations operate their semiconductor transistors as switches that, if ideal, would not dissipate any power, making these amplifiers theoretically capable of achieving 100% drain efficiency. However, semiconductor transistor switches are not sufficiently ideal to allow these power amplifiers to achieve their efficiency potential. Instead, their finite series resistance, large input capacitance, nonlinear drain capacitance, substrate losses, voltage limitations, and temperature dependencies all contribute to lower effective efficiency. To achieve a more ideal efficiency for power amplification configurations, researchers at UC Berkeley have developed a switch design that reduces or eliminates many of the efficiencies of semiconductor transistor switches. In overcoming the long-standing impasse in power amplifier advancement, this innovative switch has the potential to open many new opportunities that include not only an increase in the talk-time of portable battery-powered wireless transceivers, but also a significant increase in the range of high power transmitters. The higher efficiency enabled by this Berkeley switch reduces the power dissipated in the amplifier itself, thereby lowering its temperature and allowing a further increase in output power -- that is further accommodated by the large voltage handling capability and better temperature resilience of the switch. The net result is a high power transmitter in a smaller and lower weight package. (more...)

Berkeley Lab and UC Berkeley researchers have invented a plastic microfluidic chip with integrated interconnects. The researchers use inventive mold-making and injection molding processes to fabricate disposable chips with integrated ports that accommodate commercially available male fittings and can withstand pressures over 35 MPa. The ability to perform at these pressures enables the inclusion of porous materials inside the chip channels to increase surface area and provide functionalization, an ability that previously has been limited by interconnect reliability. Monolithic integration of the ports also eliminates the need for extra fabrication steps and contaminating bonding agents. The novel chip is injection molded as two parts and then thermal fusion or solvent vapor bonded. The inventors have optimized the parameters of the processes to maintain channel shape and ensure a strong bond, achieving low standard deviations in a series of fabrications. The ports have ANSI-standard internal threads to allow a high-pressure reversible fluid connection between micrometer-scale capillaries and the chip ? a connection that facilitates replacement of capillaries damaged at the capillary/chip junction. The ability to accommodate standard fittings also allows users to easily connect the chip channels with commercially available chromatography equipment. The designs are fabricated from a plastic with low background florescence, which enables the use of laser induced fluorescence (LIF), a very sensitive detection technique. The material's high transmission to ultraviolet (UV) and deep-UV light allows the channel walls to be patterned using UV light. (more...)

As micro- and nano-scale electromechanical systems become commercially established, the widespread success of these products will be hindered unless testing methods and standards are developed to measure the properties of these products. Currently, the lack of testing methods and standards makes it difficult for customers to specify their requirements, and manufacturers to specify the properties of their products. Furthermore, testing standards for these micro- and nano- scale products are difficult to develop because they are prone to numerous uncertain properties due to their extreme sensitivity to process variations in how they are both fabricated and tested. While a few testing standards exist, their relatively high costs, long duration and uncertain accuracy make them nonideal for facilitating the growth of these emerging products. To address these issues, researchers at UC Berkeley have designed an electromechanical device and developed associated analysis techniques that make the measuring of micro- and nano- scale systems commercially viable. This compact device can fit inside a 1 mm by 1 mm square or smaller. It can accurately measure in-plane over- or under- cut, effective Young's Modulus, and the comb-drive force for the material and process in which it was made. In contrast to other similar techniques, this device and the methods used to measure properties are more accurate and economical. (more...)

Most micro-sensors and integrated circuits are made using silicon, and most metallic structural materials and devices are made using steel. Accordingly, the capability to bond Si-based sensors and circuits to steel-based devices and structures could lead to many potential applications. However bonding these two materials without damaging either of them is difficult. Furthermore in order to make the bonded product cost-effective, the bonding must be performed in seconds on an assembly line process. The conventional method for bonding devices to steel is by using epoxy adhesive, but the cure time is long, the modulus of elasticity is low, and the resilience in harsh environments is questionable. To address this problem, researchers at UC Berkeley have developed an innovative method for bonding silicon to steel. This method's bonding temperature is low enough to not damage the steel's heat treatment or the silicon part; and the bonding is achieved in seconds. Moreover, the bonding heat can be localized thereby reducing energy costs and possible residual heat damage. (more...)

Piezoelectric bending actuators have the potential to be used as the muscles in a variety of autonomous, micro-mechanical robotics devices under development. While commercially available bending actuators have the requisite high levels of mechanical energy for these miniature robotics applications, the mass of these existing actuators are too high -- by orders of magnitude. To address this problem, researchers at UC Berkeley have developed a new class of piezoelectric bending actuators with ultra-high energy densities. These new actuators have been optimized for low-mass applications using sophisticated math models, and their benefits are based a variety of innovative design features and fabrication methods. The actuators can be tailored for most kinematic and dynamic requirements. Whereas commercial piezoelectric bending actuators have energy densities that range from 0.15 to 0.007 Jkg(-1), and masses that range from 340 to 120,00 mg, a bimorph version of this new class of actuators exhibited an energy density of 2.5 Jkg(-1) with a mass of just 11 mg. (more...)

The unique electrical, mechanical and optical properties of nanowires and nanotubes makes them attractive in a variety of applications. However, a significant obstacle to the application of these nanostructures is the difficulty in handling, maneuvering and integrating them with microelectronics to form a complete system. In particular, current synthesis processes for silicon nanowires and carbon nanotubes require high temperatures that can damage the microelectronics on which the nanostructures are being synthesized. To solve these problems, researchers at the University of California, Berkeley have developed a process for synthesizing nanostructures at a specified location inside a room-temperature chamber. This localized selective synthesis process can directly integrate either silicon nanowires or carbon nanotubes with larger-scale systems, such as foundry-based microelectronics, and it eliminates the need for subsequent assembly processes. This innovative approach is based on localized resistive heating of suspended microstructures to activate vapor-deposition synthesis, and it yields either silicon nanowires or carbon nanotubes. The process has synthesized nanowires that grow at 1 ?m/min, are 30-80 nm in diameter, and up to 10 ?m in length; and the process has synthesized nanotubes that grow at 0.25 ?m/min, are 10-50 nm in diameter and up to 5 ?m in length. (more...)

Commercially available optical tweezers can move objects using laser light, but they are generally not used to measure forces exerted on those objects, since accurate force calibration is difficult. Research in the field of optical trapping has led to the development of optical tweezers that measure forces (transverse to optic axis) by changes in light-momentum. Force calibration is greatly simplified by using this method. However, in measuring the light force on a trapped object, it is also desirable to obtain all three vector components of that force. Representing an improvement on the light-momentum force-sensor, researchers at the University of California, Berkeley have developed an axial light-force sensor. A system incorporating the Berkeley improvement permits simultaneous measurements of the axial and transverse forces acting on a trapped particle. Like the transverse sensor, the axial force sensor is calibrated from measured constant values: the speed of light, the objective focal length, and the power sensitivity of the planar photo-diode. Thus calibration is not affected by particle shape, laser power, particle refractive index, or sharpness of the trap focus. In addition, a highly-miniaturized, ultra stable, optical trap system has been developed that should permit a low cost instrument with force-measuring capabilities for use in normal lab environments. (more...)

Researchers at the University of California, Berkeley have developed an apparatus for manipulating micro-scale objects. At the micro-scale level, adhesion forces of surface tension, and electrostatic and Van der Waals force dominate gravitational forces. Recent work has shown how adhesive forces can be used advantageously during microassembly tasks by controlling contact areas and surface tension, to ensure that microparts are reliably transferred to the target surface and released from a gripper. (more...)

Chemical and biological sensors based on microresonators have been considered viable alternatives to modern sensing systems for some time, undoubtedly because they consume less power and space than their macroscale counterparts. Existing sensors require the measurement of the response of an individual resonator for the detection of a specific compound, or a class of compounds. Large sensor arrays composed of isolated microresonators can be used to broaden detection capabilities, but the addition of the attendant electronics (arising from a larger number of system outputs) adds to the complexity of such sensors. (more...)

Researchers at the University of California, Santa Barbara have developed a surface treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions.' The ability to locally change the electric field distribution can substantially improve the performance of different kinds of devices, including high electron mobility transistors (HEMTs), light emitting diodes (LEDs), and ultraviolet detectors. In AlGaN/GaN HEMTs, for example, the electric field shaping technology allows a reduction in the peak electric field in the channel, which increases the breakdown voltage and decreases the gate leakage without harming the high-frequency performance of the transistor. For LEDs and lasers, the surface treatment can passivate lattice defect like dislocations, point defects, or sidewalls, which significantly reduces leakage current and enhances the luminous efficiency of the optical devices. The following impressive results have recently been demonstrated using the surface treatment: Breakdown voltages of deep submicron (gate length < 0.2 um) HEMTs in the range of 80-100 V or more, significantly higher than the normal of below 25 V for those gate lengths; At least 2 order of magnitude lower gate leakage in the transistors; A new record in output power density at high frequencies (>10.5 W/mm @ 40 GHz) due to the higher breakdown voltage, lower gate leakage and lack of damage introduced by the treatment. This value is more than a factor of 2 higher than the previous record. (more...)

Downscaling of MOS transistors and their use in CMOS circuits has driven semiconductor industry growth and has constantly improved integrated circuit (IC) characteristics. Although the number of transistors allowed on a single chip has increased while the price per logic function has decreased, MOS transistor dimensions are approaching physical limitations. The surrounding gate (SG) and double gate (DG) MOSFET structure offer the most promise for structures having sub-50nm channel lengths, since it can efficiently suppress short-channel effects, eliminate substrage effects, and minimize leakage currents. Although FinFET presents the most cost-effective method for implementing SG and DG MOSFET structure, all existing Fin FET structures suffer from several limitations, such as degraded channel mobility on the active sidewall surfaces, low current drivability per ship area, large parasitic series resistances, high-cost, and difficulty in integrating with bipolar process for BiCMOS circuits. (more...)

A novel approach to designing high-performance nonpolar quantum wells. (more...)

A novel method for growing high-quality thick films of a-plane GaN suitable for use as substrates in homoepitaxial device layer regrowth. (more...)

A light-emitting diode (LED) is a semiconductor device that emits visible light when an electric current passes through it. Traditionally, LEDs were made with inorganic materials. However, inorganic semiconductor LEDs lack ease of processibility on large and flexible substrates. In the last decade, Organic LEDs (OLEDs) have become very popular with their diversity, easy processibility and possibility of fabrication on flexible and large area displays. But organic LEDs suffer from fundamental issues of stability and color purity. In addition, both LEDs and OLEDs lack easy color tunability. Therefore, researchers have started to experiment with Hybrid Organic-Inorganic Light Emitting Diodes. (more...)

Multipliers for digital signal processing (DSP) applications widely use the well-known modified Booth-encoding algorithm due to its ability to reduce the number of partial products. As the interconnect power dissipation begins to dominate in deep sub-micron designs, the regular structure of the carry-save array makes it the preferred method for partial-product reduction. (more...)

A novel etching process that utilizes photo-generated holes to permit the electrochemical etching of a material, such as a III-Nitride, under conditions with which it would otherwise not etch. (more...)

Self-assembled quantum dots (QDs) have been the subject of great interest in recent years due to their attractive electronic and optical properties. QD structures and their applications, such as lasers detectors, and memories have demonstrated several unique physical properties. The self-assembled growth of the QDs relies upon strain-induced island formation by the Stranski-Krastanow growth mode. However, efforts to understand and control island formation, ordering, and positioning are still limited. This lack of control of island formation, particularly with regard to island positions, presents a significant obstacle to the incorporation of QDs into novel devices. (more...)

For deep sub-micron (DSM) designs, wiring delays have exceeded transistor delays and become the dominant factor in determining overall circuit performance. To achieve minimal wire delay, a number of techniques have been introduced that use continuous or discrete wire widths selectively in an interconnect structure. These techniques, however, tend to complicate the layout design considerably (especially for detailed routing) due to the use of many wire widths. (more...)

Due to the lack of availability of crystalline GaN substrates, epitaxy of GaN is most commonly performed on sapphire or silicon carbide substrates. GaN of comparable quality has been achieved on both types of substrates using a two step growth process. The process involves depositing a thin AIN or GaN layer at temperatures between 400 and 900 C, ensuring a complete wetting of the sapphire or SiC substrate, followed by the deposition of the main layer at temperatures above 1000 C. Depending on the actual growth condition, GaN layers with dislocation densities between 108 to 109 cm-2 can be obtained.  A process known as lateral epitaxial overgrowth (LEO) was developed to improve the structural properties of such GaN layers. In this method, the GaN layer is partially covered with a mask. Growth starts exclusively in the remaining openings and the layer laterally overgrows the mask regions. Almost dislocation free material is obtained above the masked regions but dislocations remain above the open areas and at the intersections of merging growth fronts. The procedure can be repeated to deal with the remaining dislocations by placing the mask on the former openings and intersections. The resulting GaN epitaxial layers are of high quality, but the fabrication process involves several alternating growth and processing steps and very thick GaN films are deposited. These problems make the LEO approach very expensive and may limit its application to devices whose properties are extremely sensitive with respect to the presence of dislocations. (more...)

A powerful process to etch group III nitride heterostructures at room temperature. (more...)

Quantum dots possess unique properties that could potentially revolutionize existing optical and electronic technologies as well as open up new technologies. Conventional quantum dot fabrication techniques, however, have several drawbacks, such as large recombination velocities and surface depletion, that arise from having the surface exposed while patterning the substrate before or after growth. Researchers at the University of California have developed a quantum dot fabrication process that does not require any processing steps either before or after growth and so avoids typical problems such as surfaces, dislocations, and surface states. This process produces uniformly sized quantum dots in single or multiple layers out of any semiconductor, metal, or oxide material system that allows consecutive epitaxy and has lattice mismatch. (more...)