N-polar III-N Semiconductor Device Structures Enabled by Wet Chemistry

Tech ID: 31967 / UC Case 2020-703-0


Current techniques for fabricating GaN-based semiconductor devices rely on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers. Consequently, the nature of the plasma generated for dry etch processes is known to result in both surface and subsurface damage from exposure to high-energy charged ions and electrons. Due to the chemical stability of metal-polar surfaces, dry etching is the only viable approach to etch metal-polar surfaces. Additionally, these metal-polar devices have demonstrated limited RF capabilities relative to N-polar transistors fabricated by dry etch techniques. Thus, overcoming dry etching limitations would allow for drastic improvement of N-polar III-N device performance while also reducing manufacturing costs. 


Researchers at the University of California, Santa Barbara have developed wet etch processes that can be used to fabricate N-polar III-N transistors to reduce trapping effects, lower leakages, lower noise, and increase reliability. N-polar surfaces are more reactive relative to metal-polar surfaces enabling this technique. Furthermore, N-polar GaN transistors demonstrate superior RF performance, particularly at mm-wave frequencies relative to metal-polar transistors. In addition to lowering capital costs as a result of a simplified infrastructure, wet etching also reduces manufacturing cost with batch processing that can scale between different substrate sizes more easily than with dry etching. Therefore, this invention allows for the fabrication of higher performance devices in a simplified and cost-efficient manner.


  • Improves device performance
  • Reduces costs
  • Commercially scalable


  • III-N Devices
  • GaN Transistors

Patent Status

Patent Pending


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Other Information


wet etch, III-N, N-polar, semiconductor, transistor

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