High-Performance Clock Grid Synthesis and Tuning Using Distributed LC Resonant Tanks

Background

Clock signals in digital systems are simultaneously distributed to physical remote locations across an integrated circuit (IC). The clock signal provides a time reference that permits different parts of a circuit to operate in the correct order, thereby producing correct logical operation. Clocking large digital chips with a single high-frequency global clock is becoming an increasingly difficult task. Increasing clock latency in distributing the global clock from a single synchronizing source leads to problems with uncompensated skew, the difference in the clock arrival times between sequentially adjacent registers and jitter, and that which occurs at edges of the clock signal when it fluctuates in time. These problems are primarily due to intra-chip variability and power-supply noise coupling through buffers.  

Skew and jitter have traditionally been the dominant concerns in clock design; however, due to increase clock capacitance and frequency in highest-performance microprocessors, dynamic power dissipation is exploding. During every cycle, the entire clock capacitance is charged to the supply voltage, and when this charge is subsequently dumped to ground, all the stored energy is lost as heat.

Description

The new  methodologies developed by UCSC researchers undertake the unique challenges of synthesizing the resonant grids in high performance systems.  Chip design methodology enhances the usefulness of a resonant clock by achieving additional power savings, along with residual benefits through the automation of current hand tuned processes.   The on-chip clock distribution network (CDN) consumes in excess of 35% of total chip power and occasionally as much as 70%. Experimental results, in using this methodology, show CDN power savings as much as 80%. The power savings along with automation enhancement feature are technology improvements which will enable enhanced IC performance.

Applications

• Designing VSLI clock distribution networks

Advantages

Patent Status