Portable electronic devices require long battery lifetimes which can only be obtained by utilizing low-power components. Recently, low-power design has become quite critical in the System-on-chips (SOCs) because interconnect in scaled technologies is consuming an increasingly significant amount of power. Researchers have demonstrated that the major consumers of this power are global buses, clock distribution networks (CDNs) and synchronous signals in general. In addition to power, interconnect delay poses a major obstacle to high-frequency operation. Technology scaling reduces transistor and local interconnect delay while increasing global interconnect delay. Moreover, conventional CDN structures are becoming increasingly difficult for multi-GHz ICs because of skew, jitter, and variability are often in proportional to large latencies. Prior to and in early CMOS technologies, current-mode (CM) logic was the attractive high speed signaling scheme. CM schemes have been used for long global wires or, more commonly, off chip signals. Standard logic signals, however, have remained in voltage mode (VM), to benefit from low static power of CMOS Logic. Researchers at University of California, Santa Cruz, have proposed a scheme with utilizes the power and reliability of CM signaling and yet retain compatibility with low-power CMOS logic.