There is no question that electrostatic discharge (ESD) failure is currently one of the most devastating integrated circuit (IC) reliability problems. A reliable on-chip ESD protection method is required to protect ICs against various ESD damages, and charged device model (CDM) ESD protection design has emerged as a new challenge for ICs at the most advanced technology nodes. Vast efforts have been devoted to understanding the CDM ESD failure mechanisms and developing solutions, but it is commonly agreed upon that it has yet to be accomplished.
Prof. Albert Wang and colleagues from the University of California, Riverside have developed an effective and reliable method for designing an internally distributed CDM ESD protection network. This technology works by having the ESD protection network distributed inside the silicon substrate. Existing CDM ESD protection methods use external pad-based ESD protection to channel discharge in a pathway known as “from-external-to-internal” which leads to CDM ESD failures. This technology is superior to current methods because the discharge is directed “from internal-to-external” and solves the fundamental issues that cause existing CDM ESD protection methods to fail.
Fig 1: Illustration of the pad-based global ESD protection network on an IC chip where ESD protection devices are connected to each pad to ensure an ESD discharging path between pads on a chip.