UCLA researchers in the Department of Electrical and Computer Engineering have developed a magnetoelectric memory device that uses two dielectric barriers for improved voltage-controlled magnetic anisotropy (VCMA) and tunnel magnetoresistance (TMR) properties.
New random-access memory technologies, such as magneto-electric random-access memory (MeRAM), have been emerging as computer data storage must keep up with the increasing amount of data being generated and processed. MeREAM uses voltage to manipulate and switch magnetization directions and is also referred to as a magnetoelectric junction (MEJ) device. Controlling the switching direction in MEJ devices is a key requirement for the realization of practical MeRAM products. Currently, MEJ devices use only one dielectric barrier to control the voltage-controlled magnetic anisotropy (VCMA), which switches the magnetization in the free layer, and the tunnel magnetoresistance (TMR), which reads out the magnetization. In this single dielectric layer design, the magnitude of the VCMA and TMR effect depend on the dielectric layer used, and therefore the two properties cannot be optimized independently. This design is problematic because the best material for high TMR may not be the best material for high VCMA, and vice versa.
UCLA researchers have developed a magnetoelectric device with two dielectric barriers to realize the independent optimization of VCMA and TMR properties. One dielectric layer provides high VCMA for a low switching voltage. The other dielectric layer provides high TMR for readout of the magnetic state of the free layer. The overall combination of the VCMA and TMR effects in the device may be improved as a result of using two barriers, compared to the single-barrier MEJ architecture. The MEJ devices described here may also be used in crossbar and non-crossbar memory architectures. The resulting circuit can be integrated into a larger circuit, system on chip, memory, or logic circuit. Moreover, it can be tested using existing memory techniques, such as bit-level testing of switching properties.
|United States Of America||Issued Patent||9099641||08/04/2015||2014-140|
free layer magnetization, magneto-electric random-access memory (MeRAM), voltage-controlled magnetic anisotropy (VCMA)-induced switching, magnetoelectric junction device, tunnel magnetoresistance (TMR), dielectric layer