UCLA researchers in the Department of Electrical and Computer Engineering have developed a digital spur cancellation technique for frequency synthesizers used in clock synchronization.
As wireless applications become more diverse and sophisticated, time synchronization between communication endpoints is an emerging requirement. Moreover, size, cost, and design complexity considerations render the need for low power, compact, and, low jitter clock signals at different frequencies from a single reference oscillator. Analog or digital phase-locked loops (PLL) can generate clock signals with low jitter and spur levels. Frequency synthesizers based on digital-to-phase or –time converters (DPCs) are compact and low power, but circuit errors and mismatches result in strong spurious tones. Thus, there is a need for clock synchronization that implements a spur cancellation technique.
UCLA researchers have developed a digital spur cancellation technique that extracts spurious tones precisely and digitally corrects for them. When this spur cancellation technique is applied to a DPC-based frequency synthesizer it achieves integrated jitter <90fs and spurious tones 33dB better than the leading prior art. Moreover, the measured spur levels are limited only by the instrument noise floor. The technique achieves at least 29dB lower spurious tone, and 8x lower integrated rms jitter for lower power consumption. Thus, this digital spur cancellation technique can be readily applied to multi-clock generators with improved jitter and spur levels.
Multi-Output Fractional Frequency Synthesizer, digital-to-phase or –time converters (DPCs), digital spur cancellation, jitter, spurious tones, DPC-based frequency synthesizer, clock synchronization