UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel ultra-low power crystal oscillator architecture that achieves the lowest reported power consumption.
Crystal oscillators (XOs) are high-Q resonators that are widely used in electronics systems to generate the reference clock signal. Ultra-low power (ULP) consumption of the XO is critical in highly duty-cycled, energy-constrained systems such as Internet-of-things (IoT). Conventional XOs, typically implemented in the Pierce configuration, consume high power to ensure frequency stability over process, voltage, and temperature (PVT) variations. Recently reported low power XO designs often require high-power components, complicated designs with multiple power domains to properly time the pulses, or significant calibration and off-chip components to reduce PVT sensitivity.
Researchers at UCLA have developed a novel ULP XO architecture that achieves the lowest reported power consumption of 0.55 nW from a 0.5 V supply. The described architecture employs a DC sustaining amplifier instead of one at the crystal’s resonance frequency, thus requiring significantly less power. Furthermore, the described XO oscillates at its series-resonance frequency, which improves its frequency stability even without large load capacitors.
A proof-of-concept prototype is available.