Advanced All-Digital Phase-Locked Loop (ADPLL) Control System for Electronic Timing and Synchronization

Tech ID: 24941 / UC Case 2015-078-0

Summary

Researchers in the UCLA Department of Electrical Engineering have designed an advanced all-digital phase-locked loop (ADPLL) control system that improves signal quality and reduces power consumption for signal timing and synchronization functions in high-performance telecommunications and radar electronics.

Background

Phase-locked loops (PLLs) are essential circuits used for a variety of timing, synchronization, and signal processing functions in a range of electronic systems. An important application of PLLs is in telecommunication and radar systems, where they are used to generate the carrier frequencies, local oscillator frequencies, and intermediate frequency signals. The present trend in both wired and wireless communication and radar systems is towards the use of all-digital PLLs (ADPLLs), which offer the advantages of smaller chip size, better scalability, and extensive re-configurability compared to traditional (analog) PLLs. However, the performance of ADPLLs remains limited by the in-band phase noise that results from the finite temporal resolution of the available time-to-digital converters (TDCs) on which they rely. The purpose of TDCs is to assign digital “time stamps” to events of interest. Like all digital values, these time stamps represent approximations of true event times – the higher the TDC’s resolution, the better the approximation. The discrepancies between the true and digitized time values manifest as imprecision (noise) in the ADPLL’s output signal. Therefore, TDCs with higher temporal resolution can lower the noise and thus improve the signal quality of ADPLLs.

Innovation

Professor Frank Chang in the UCLA Department of Electrical Engineering has developed an advanced all-digital phase-locked loop (ADPLL) control system, wherein the time-to-digital conversion (TDC) is performed by an analog-to-digital converter (ADC) using a sampling frequency significantly lower than the input signal frequency. This “sub-sampling” technique improves the TDC’s temporal resolution while reducing its power consumption, thus enabling a low-noise, low-power, high-performance ADPLL.

Applications

  • Telecommunications System Electronics (wired & wireless) – Specific functions include:
    • Coherent De-modulation
    • Threshold Extension
    • Bit Synchronization
    • Symbol Synchronization
  • Radar System Electronics
    • Radio Transmitters Signal Generation
  • Computing
    • Microprocessor Clock Multipliers
    • Clock Timing Information Recovery
    • Digital Signal Processing of Video Signals

Advantages

  • Low noise
  • Low power consumption
  • Small chip size
  • Scalability
  • Re-configurability

State Of Development

  • UCLA researchers have validated the reported ADPLL circuit design using virtual simulation

Patent Status

Patent Pending

Contact

Inventors

  • Chang, Mau-Chung Frank

Other Information

Keywords

All-digital phase-locked loops (ADPLL), time-to-digital conversion (TDC), analog-to-digital conversion (ADC), telecommunications, wireless technology, radio communication, radar, signal modulation & demodulation, modems, computing,, high-frequency electronics, synchronization, microprocessor clocks & timing, signal processing

Categorized As