Micro Electromechanical Switch Design with Self Aligning and Sub-Lithographic Properties

Tech ID: 23092 / UC Case 2013-082-0

Brief Description

Shrinking of integrated circuit (IC) device dimensions provides for enhanced functionality and performance  of computers and electronics. Researchers at Berkeley are exploring nano-mechanical information processing as a means to overcome the energy-efficiency limits of CMOS technology and recently have directed their efforts toward the development of device designs suitable for implementation in the cross-point array architecture for minimal footprint. 


To that end, our researchers have designed a novel process for fabricating ultimately scaled electro-mechanical relays with decananometer lateral dimensions. Their innovation includes a compact electro-mechanical switch design which has self-aligned features with a minimum dimension not defined lithographically. By incorporating multiple sets of output electrodes, the area required to implement a complex logic gate is reduced by a factor of 2. 

Suggested uses

  • Ultra low power and low cost ICs
  • Suggested applications include battery-life dependent electronics and displays, safety-critical devices (e.g. medical devices), nanotechnology, power management and energy harvesting applications


  • Design structure possesses property desirable to overcome hysteresis limitation of contacting mechanical switches
  • Air-gap based mechanical switches have zero sub-threshold leakage current, rendering trade-off between decreasing active energy and increasing leakage energy non-existent
  • Allows logic gate implementation with smaller footprints than equivalent CMOS implementation

Related Materials

  • Publication: Y.-K. Choi, T.-J. King, and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp. 436-441, 2002.


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  • King Liu, Tsu Jae K.

Other Information


integrated circuit, electronics, computer, nanotechnology, CMOS, EDA, design

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