UCLA researchers in the Department of Electrical Engineering have developed a novel power-optimal dual-Vdd buffered tree and fast algorithms for power-optimal buffering.
Aggressive scaling of VLSI circuits makes interconnects the performance bottleneck, and buffer insertion is used extensively to reduce interconnect delay at the expense of more power dissipation. Interconnect optimization is a critical component of typical VLSI design flows for timing closure.
The invention has an innovative concept of applying dual-Vdd inside a routing tree, including buffer insertion for given tree topology and buffered tree. An algorithm to tackle the power-optimal buffer insertion and buffered routing tree construction problems using dual Vdd buffers is also disclosed. The algorithm improves on the current state of the art by using three speed-up techniques to obtain an effectively linear time algorithm.
Complex VLSI circuit design Power minimization within Dual Vdd buffer circuitry
The invention has been experimentally verified.
|United States Of America||Issued Patent||7,877,719||01/25/2011||2005-733|