Power-optimal Dual-Vdd Buffered Tree and Fast Algorithms for Power-optimal Buffering

Tech ID: 20388 / UC Case 2005-733-0


UCLA researchers in the Department of Electrical Engineering have developed a novel power-optimal dual-Vdd buffered tree and fast algorithms for power-optimal buffering.


Aggressive scaling of VLSI circuits makes interconnects the performance bottleneck, and buffer insertion is used extensively to reduce interconnect delay at the expense of more power dissipation. Interconnect optimization is a critical component of typical VLSI design flows for timing closure.


The invention has an innovative concept of applying dual-Vdd inside a routing tree, including buffer insertion for given tree topology and buffered tree. An algorithm to tackle the power-optimal buffer insertion and buffered routing tree construction problems using dual Vdd buffers is also disclosed. The algorithm improves on the current state of the art by using three speed-up techniques to obtain an effectively linear time algorithm.


Complex VLSI circuit design Power minimization within Dual Vdd buffer circuitry


  • 17x speed up (without implementation of fast algorithms) with little loss of optimality compared to current methods
  • Dual-Vdd buffers reduce power by 23% at the minimum delay specification compared to buffer insertion with single Vdd buffers
  • Compared to the delay-optimal tree using single Vdd buffers, the power-optimal buffered tree designed at UCLA reduces power by 7% (single Vdd buffers) and 18% (dual Vdd) buffers at the minimum delay specification
  • By implementing fast algorithms, 50x and 100x speedup are obtained compared to the most efficient existing algorithms for dual Vdd buffer insertion and buffered tree construction respectively

State of Development

The invention has been experimentally verified.

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 7,877,719 01/25/2011 2005-733


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  • He, Lei

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