Suspended structures enable control of p-n or n-p-n junctions- the interfaces between diodes, transistors and other semi-conductor devices. However, fabrication of suspended structures using most current techniques is extremely difficult because direct deposition of dielectrics (or ‘insulators’) can stress or even collapse the thin graphene layers employed in these devices.
UC researchers have developed a novel technique for fabrication of suspended structures on graphene (Figure 1). The UC technique makes it easier to fabricate a suspended top gate over the semi-conductor substrate and back gate. The top gate makes it easier to apply local electric fields that enhance mobility in graphene p-n and n-p-n junctions.
Figure 1: Suspended
top gate structures
The UC technique offers the following advantages relative to existing techniques:
The UC technique ensures that the graphene devices formed do not suffer from undesirable defects that arise from deposition of intervening layers that involve introduction of impurities and dopants. The technique does not require etching of sacrificial (or ‘resist’) layers, which may inadvertently edge other components during fabrication.
The new UC technique can also be applied to fabrication of other types of devices that are highly sensitive to process-induced damage. These devices may include sensors for detection of local magnetic fields and micro-electrochemical (MEM) devices with moving parts such as resonators.
The UC technique can also be used to induce local magnetic fields, which can be employed in conjunction with magnetic media for data storage. The localization of magnetic fields eliminates the need for a read/write head that moves over the surface of the magnetic media. The use of high density array of suspended structures using the UC technique may result in production of high density magnetic storage devices.
|United States Of America||Issued Patent||7,948,042||05/24/2011||2008-481|