Circuits, Architectures And CAD Algorithms For Power Efficient FPGAs

Tech ID: 21688 / UC Case 2004-645-0

Summary

Researchers at UCLA have developed a FPGA design that significantly reduces power consumption while remaining compatible with conventional FPGA designs.

Background

While FPGAs are attractive design platforms due to their low cost and short time to market, their power efficiencies are much lower than that of traditional ASIC designs. Currently, many of the power optimization techniques proposed to overcome this problem significantly complicate the design and do not address all sources of power consumption.

Innovation

Researchers at UCLA have developed a simple and effective FPGA design methodology for low-power applications. Through selectively applying a lower power supply to unused logic blocks and interconnects, the proposed method reduces the total power consumption, without requiring complicated power-reduction blocks.

Applications

Digital Signal Processing
Image Processing
Aerospace & Defense
Communication Systems
Medical Imaging
Cryptography

Advantages

Reduced Power Consumption (50% Reduction Observed)
Extremely Low Utilization Rate
Compatible with Traditional FPGA Layout
Does Not Overly Complicate the CAD Flow

State Of Development

Circuit simulation shows potential power reduction of 2x to 5x compared to existing FPGA chips without Vdd programmability

Patent Status

Country	Type	Number	Dated	Case
United States Of America	Issued Patent	7,714,610	05/11/2010	2004-645
United States Of America	Published Application	20100281448	11/04/2010	2004-645

Related Materials

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, F. Li, Y. Lin, L. He, J. Cong, International Symposium on Field Programmable Gate Arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays table of contents (2004)
Vdd programmability to reduce FPGA interconnect power, F. Li, Y. Lin, L. He, Computer Aided Design, ICCAD-2004, IEEE/ACM International Conference (Nov. 2004)
FPGA power reduction using configurable dual-Vdd, F. Li, Y. Lin, L. He, Annual ACM IEEE Design Automation Conference, Proceedings of the 41st annual Design Automation Conference (2004)

Inventors

He, Lei

Contact

UCLA Office of Intellectual Property & Industry Sponsored Research / ncd@research.ucla.edu / tel: View Phone Number. Please reference Tech ID #21688.

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Other Information

Categorized As

Semiconductors
- Design and Fabrication

Related cases

2004-645-0

Keywords

computer hardware, electrical, FPGA