BACKGROUND

In current vertical gate-depleted single electron transistors, the mesa must be etched to the point just below the tunneling barrier. In addition, the gate Schottky contact must wrap the pillar containing the tunneling barriers. These requirements considerably complicate the processing of these devices.

DESCRIPTION

Scientists at the University of California have developed a novel approach to fabricating these devices which greatly simplifies the process while allowing the gate to be split into multiple gates.

Suggested uses

ADVANTAGES: The new UC technology provides the following benefits:

• Easier to interconnect than present devices;
• Increased integration density and improved performance;
• Allows for gate-splitting architectures;
• Simplifies the fabrication process.

Patent Status

Country	Type	Number	Dated	Case
United States Of America	Issued Patent	7,547,932	06/16/2009	2002-421

Inventors

• Baron, Filipp A.
• Wang, Kang-Lung L.
• Zhang, Yaohui

Contact

Ben Chu / bchu@research.ucla.edu / tel: View Phone Number. Please reference Tech ID #10257.

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Other Information

ADDITIONAL TECHNOLOGIES BY THESE INVENTORS

• Relaxed SiGe Films By Surfactant Mediation
• Horizontal Current Bipolar Transistor
• High Aspect Ratio FinFET For High-Density CMOS/BiCMOS Applications
• High Aspect Ratio FinFET
• Novel Nanomaterial-based Thermo-Photovoltaic Cells
• Horizontal Current Bulk Bipolar Transistor
• Ordered And Self-Assembled MnXGe1-X Nanostructures By MBE
• Graphene Flash Memory Device
• Vertical-Stacked-Array-Transistor (VSAT) for Nonvolatile Memory Devices
• Vsat Structure For Nonvolatile Memory Device

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