Researchers led by Jason Cong from the Department of Computer Science at UCLA have developed an improved on-chip crosstalk noise model to optimize integrated circuit design.
Integrated circuits (IC) have become smaller and smaller over the years to suit our technological and processing needs. The components of IC’s are now sub-micron distances apart. This small distance between components and interconnects give rise to “crosstalk” noise that decrease the performance of the IC and has now become an important feature to keep in mind when designing IC’s. To incorporate noise in IC design, designers use mathematical models of noise to come up with IC designs and geometries that will minimize noise. However, current models of noise are overly simplistic or use unrealistic assumptions which lead to either underestimating or overestimating crosstalk noise. Additionally these models only take into account peak noise and do not include modeling of the noise width.
Researchers led by Jason Cong from the Department of Computer Science at UCLA have developed an improved on-chip crosstalk noise model to optimize integrated circuit design. Their model characterizes not only peak noise in an IC like previous models, but it also characterizes noise width. It takes into account many parameters that previous models have not like, aggressor slew, coupling locations (e.g. near-driver or near-receiver), and distributed detailed RC characteristics (e.g. downstream/upstream interconnect resistance/capacitance, etc.). Even though this model takes into account more features, its complexity is still the same as previous noise models. IC designers that use this model can enjoy more efficient noise-aware interconnect design, better IC performance, and shorter design time due to the accuracy of their noise model.
|United States Of America||Issued Patent||7,013,253||03/14/2006||2000-244|
integrated circuit, crosstalk noise, noise, interconnect, CAD, design, optimization, minimization, modeling, noise reduction, fabrication