The Device Research Laboratory at UCLA’s Electrical Engineering and Computer Science Department has developed the first specialized control circuit for VCMA-based MRAM devices that is high-speed, low error, and low power.
Magnetoresistive random access memory (MRAM) is a new form of non-volatile random access memory that could replace all current memory technologies as a form of “universal memory.” Consumer electronic devices are currently designed using SRAM, DRAM, or flash memory. SRAM and DRAM offer the highest speeds and storage but require constant power to maintain data retention, making them power hungry technologies. Flash memory is a non-volatile (i.e. data is retained even when power is off) alternative that consumes less energy with high speed and scalability. Flash technology is limited by a finite number of read/write cycles before hardware deterioration occurs as a result of the large charge pump required to write data. MRAM technology offers the potential advantages of greater storage, higher speed, longer endurance, and lower energy consumption of the aforementioned technologies without their disadvantages. While continued advances to current memory technologies have delayed the emergence of MRAM, continued development to improve its capabilities will accelerate its mainstream adaptation.
The Device Research Laboratory, under the direction of Prof. Kang Wang, has developed a high-speed, low-power pre-read and write sense amplifier (PWSA) circuit for MRAM capable of fast read/write cycles, reduced bit error rates (BER), and lower energy requirements compared to existing MRAM designs. By incorporating a pre-read and comparison step, the PWSA is able to reduce power consumption by 50% and BER under random input conditions by eliminating redundant writes. This technology also represents the first specialized circuit utilizing voltage controlled magnetic anisotropy (VCMA) precessional switching. VCMA which offers a greater than 10-fold reduction in write power and transistor size in both the memory cell and write circuit compared to conventional spin transfer torque (STT) control. This is important as power and component size reductions are critical to addressing current demands for greater device miniaturization and energy efficiency for consumer devices.
PWSA circuit schematic proposed and results verified in simulations.
|United States Of America||Issued Patent||9,672,886||06/06/2017||2014-834|
Magnetoresistive random access memory, MRAM, voltage controlled magnetic anisotropy, VCMA, spin transfer torque, STT, non-volatile random access memory, NAND, Flash memory, nvRAM