Researchers at the University of California, Davis have developed a quarter-rate serial link receiver with low aperture delay samplers for use in high-speed serial link interconnects in network systems. This receiver decreases the parasitic capacitances that result from threshold adjustments and can drastically decrease the amount of power required for high data rate applications.
Serial links are used for connections between chips in networked systems and are important in multimedia sharing, cloud computing, virtual reality (VR) and other high use network systems. Traditional serial link receivers use equalizers, for example, half rate continuous-time linear equalizer (CTLE) with decision feedback equalizer (DFE), to reduce inter-symbol interference (ISI). Next-generation data rates, however, will require higher speeds and the currently employed half rate receivers will be inefficient and require more power.
Researchers at the University of California, Davis have designed a quarter-rate serial link receiver with much lower aperture delays in the samplers for use in high date rate applications. This design ensures that almost no noise affects the data and that the power consumption of the serial link is unchanged due to the increased speeds by utilizing offset calibration and DFE threshold adjustment. The full quarter-rate architecture saves more than a half of power consumption compared to half-rate architecture and the combination of DFE threshold adjustment and the sampler offset calibration improves system performance without introducing excessive parasitic capacitance. This new scheme has been successfully simulated and confirmed to achieve better eye-open performance while consuming less power compared to traditional half rate equalization.
serial link receiver, networked systems, half rate continuous-time linear equalizer, CTLE, decision feedback equalizer, DFE, inter-symbol interference, ISI, parasitic capacitance, high data rate application, high-speed serial link