Data Shepherding: Cache Design For Future Large Scale Chips

Tech ID: 28786 / UC Case 2017-413-0

Brief Description

The ability of a central processing unit to store frequently-used data in nearby, easily accessible cache data banks has revolutionized computational performance, though their effective implementation in multicore processors has become a technological challenge. Researchers at UCI have developed a new means of data caching that is fully applicable to multicore processors, and offers reduced memory access time over standard techniques.

Full Description

Tiled cache architecture suffers from access latencies between individual cores and shared cache slices, particularly at the last level shared cache (LLSC), which increases memory access time and slows down computational performance. Additionally, traditional tiled cache design is not compatible with predicted trends in chip design (e.g., 3D integrated circuits, heterogeneous workloads, etc.). The invention describes a data shepherding cache memory (specifically for LLSC), in which a cache block is shared and tracked via cache coherence protocol implemented between cores. This protocol is accomplished with the help of the virtual memory system mechanism inherent to the device operating system (OS). The result allows for specific data to be identified and located within cache banks quickly and effectively. This invention also provides a means for scalable cache design that is compatible with the future of chip architecture, all without increasing memory access time.

Suggested uses

• Computer architecture • For implementation in multicore devices utilizing tiled cache design.sdf

Advantages

• Data shepherding cache design is fairly general, and so is compatible with advances such as 3D integrated circuits • Design minimizes latency associated with memory retrieval in LLSC of tiled cache multicore arrangements • Utilizes existing mechanisms embedded in standard device OS

Patent Status

Patent Pending

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Other Information

Keywords

Cache design, tiled cache design, last level shared cache, multi-bank cache design, shared coherent TLB, 3D stacked architecture

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