Tru-Wafer Interconnects For Mems Double-Sided Fabrication Process

Tech ID: 25655 / UC Case 2015-218-0

Brief Description

-High aspect ratio, low resistance thru-wafer interconnects for double-sided MEMS


o Enables efficient manufacturing of thru-wafer interconnects

o Technology is compatible with standard semiconductor processing

o SOI inertial sensors and interconnects fabricated on wafer level in one process

Full Description

This is a method for high aspect ratio, low resistance thru-wafer interconnects for double-sided (TWIDS) fabrication of MEMS where the SOI (silicon on insulator) inertial sensors and interconnects are fabricated on wafer level in one process. The interconnects are formed by etching via holes into an SOI wafer. The holes are then filled with copper using a sonic-assisted seedless copper electroplating method. Donut-shaped gaps are then etched around the copper filled vias to provide insulation. The method is an improvement over older processes in filling the high-aspect ratio via holes with a high-conductivity material (in this case, copper) without void formation in the interconnects. TWIDS can be incorporated while avoiding deposition of multiple layers and enables utilization of both front and back side of a wafer, allowing for co-fabrication of released SOI sensors and thru-wafer interconnects on wafer level in one process. TWIDS technology is compatible with standard semiconductor processing, and suitable for co-integration with released SOI sensors, such as MEMS accelerometers, gyroscopes and clocks.


The footprint of MEMS devices can be greatly reduced by making use of the z-dimension in packaging MEMS devices. 3D packaging involving the stacking of wafers and creating electrical connections between them is the next step in the continuous effort to increase performance while decreasing size. Through-wafer interconnects are an efficient way to make these connections between stacked wafers and avoid problems of traditional wire bonding.

Previous methods for developing thru-wafer interconnects and making the via, which are the vertical electrical connections in the wafer, can be divided into two groups. The first is one where the interconnects are formed by the wafer material and the via are created by patterning and etching the silicon wafer to create a recess, then filling the recess with an insulator material, removing the excess silicon, and finally depositing a thin metal layer on the silicon parts. The second is one in which a vertical via hole is formed using a form of deep reactive-ion etching, then covered in an insulating layer and finally a conductive layer, which can either serve as the electrical connection itself or as a seed for subsequent electroplating.

There are drawbacks to both types of methods. The first group’s interconnects have a relatively high resistance as compared to the second group’s due to the lower conductivity of silicon as compared to metal. While the second group have many beneficial qualities, such as the ability to create high-aspect ratio and ultra-low resistance interconnects, the method can be complicated by challenges in the fabrication of metal, leading to void formation in the interconnects. This technology addresses these issues and assures continuity, high aspect ratio, electrical isolation and void-free structures.

Suggested uses

o 3D packaging of MEMS devices

o 3D folded TIMU (Timing Inertial Measurement Unit)


· Void-free interconnects through use of sonic-assisted seedless copper electroplating method

· Enables utilization of both front and back side of wafer

· Compatible with standard semiconductor processing

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 9,611,138 04/04/2017 2015-218

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