Improved 3D Transistor

Tech ID: 25614 / UC Case 2016-088-0

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 10,374,086 08/06/2019 2016-088
 

Brief Description

This case helps reinvent the transistor by building on the success of Berkeley’s 3D FinFET/Trigate/Tri-Gate methods and devices, with increased focus on the negative capacitance of the MOS-channel and ferroelectrics, and an unconventional effective oxide thickness approach to the gate dielectric. Proof of concept devices have been demonstrated at 30nm gate length and allow for use of thinner ferroelectric films than 2D negative capacitance transistors (e.g. see http://digitalassets.lib.berkeley.edu/techreports/ucb/text/EECS-2014-226.pdf ). The devices also performed at low operating voltage which lowers operating power.

Suggested uses

  • Mobile/Portable electronics
  • Data centers and servers

Advantages

  • Extremely low operating voltage which lowers operating power
  • Avoids costly and unusual substrate structures common in 2D
  • Leverages conventional techniques to fabricate 3D transistors

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Inventors

  • Hu, ChenMing

Other Information

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