|United States Of America||Issued Patent||10,374,086||08/06/2019||2016-088|
This case helps reinvent the transistor by building on the success of Berkeley’s 3D FinFET/Trigate/Tri-Gate methods and devices, with increased focus on the negative capacitance of the MOS-channel and ferroelectrics, and an unconventional effective oxide thickness approach to the gate dielectric. Proof of concept devices have been demonstrated at 30nm gate length and allow for use of thinner ferroelectric films than 2D negative capacitance transistors (e.g. see http://digitalassets.lib.berkeley.edu/techreports/ucb/text/EECS-2014-226.pdf ). The devices also performed at low operating voltage which lowers operating power.