Improved Programmable Logic Circuit Architecture Using Resistive Memory Elements

Tech ID: 24667 / UC Case 2012-038-0


UCLA researchers have designed a novel FPGA architecture using resistive memory elements, which saves area and increases speed without changing architectural functions by allowing the interconnects to be entirely fabricated over the logic blocks.


A field-programmable gate array (FPGA) is known as an attractive alternative to application-specific integrated circuits (ASICs) due to its shorter design cycle and lower engineering cost. In an FPGA-based system, a design is mapped to reconfigurable logic elements and a hierarchy of reconfigurable interconnects that allow the logic elements to be connected together. The programmable interconnects are made up of connection blocks and switch blocks that take up a much larger area and higher complexity compared to the direct interconnects of ASICs, and also make up the majority of delay and power use, which can be as high as 80% of the overall circuit delay and power. With the recent development of emerging technologies, a number of novel FPGA architectures based on these technologies have been proposed in the past few years, such as 3D technologies to stack programmable interconnects over logic blocks. However, many of these methods are limited due to material-related temperature considerations both during fabrication and use, and also may require a longer and more complicated production process.


Researchers in the UCLA Departments of Computer Science and Electrical Engineering have designed a FPGA architecture using CMOS-compatible resistive memory elements and metal wires, where the interconnects can be entirely fabricated over logic elements to save area and thus also increase speed while keeping their architectural functions unchanged. Compared to the fixed buffer pattern in most programmable logic circuits, the positions of inserted buffers in the proposed architecture are optimized on demand. The number of the programming transistors for resistive memory elements is also reduced significantly. Additionally, because this design still uses standard metal wires for interconnects instead of nanowires, the problems associated with such an emerging technology are avoided. 3D stacking can be further applied to this design to achieve even greater improvements in space savings, speed, and power efficiency.


The proposed architecture can be implemented into FPGA-based circuits, which have an increasingly broad set of applications such as:

  • Switches
  • Routers
  • Servers
  • Wired and wireless communications
  • Medical and consumer electronics
  • Image processing


  • Interconnects can be placed entirely over logic elements such that the FPGA area can be reduced to that of logic blocks only.
    • Increased speeds and reduced area/power are achieved.
    • Architectural functions are unchanged.
  • Buffer insertion is on-demand, leading to to better performance with lower power consumption.

State Of Development

The proposed architecture has been modeled at the circuit level and went though a complete physical design process (using a modified physical design system developed at UCLA) on a set of benchmark examples. The results show that the proposed method brings significant area savings, power consumption savings, and faster speed compared to conventional FPGA architectures.

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 9,461,649 10/04/2016 2012-038

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Other Information


CMOS, digital integrated circuits, field programmable gate arrays, memristors, network routing, ASIC, FPGA, memristor, reconfiguration, interconnect delay reduction, logic blocks

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