Cognitive Power Management For Memory-Dominated Wireless Communication Systems

Tech ID: 23120 / UC Case 2013-374-0

Full Description

Dynamic voltage frequency scaling (DVFS) techniques is the traditional technique to perform power management where a design tradeoff is performed between power and delay where lower power is attained at the cost of larger delay, typically by running at a lower operating frequency which is set by the weakest performer in the overall system. In a majority of scenarios, the culprit is embedded memories, since they exhibit the highest vulnerability to supply changes as compared to logic. For this reason, when voltage scaling is used, memories are typically treated separately to maintain the margins such that the device will meet timing 100% of the time with the new settings. While, this is true for some applications such as processor memories, there exists a wide variety of applications that are error tolerant by design such as wireless and multimedia devices where the data structures are designed in such a way that there is redundancy inserted in the data stream to compensate for a variety of errors sources. In such systems, DVFS can’t trade-off the power saving with the forgiving nature of the system.

University researchers have developed a method for designing power management systems in embedded wireless communication devices. The invention makes use of a derived statistical correlation between memory supply voltage overscaling (VoS) and bit error rate (BER). By using this model to predict memory error rate for a given supply voltage, and knowledge about the channel error rate, the power controller may scale memory supply voltage to introduce the maximum allowable error rate given the fault-tolerance of the data structures used and the transceiver hardware. Thus, the controller may minimize power usage whilst maintaining a BER associated with the desired Quality of Service (QoS).

Suggested uses

Allows wireless transceivers to operate at a lower power level given a certain reliability requirement.

Advantages

The proposed model enables the system designers to rapidly and accurately design a more efficient power management policy as compared to the traditional power management policies such as DVFS.

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 9,785,220 10/10/2017 2013-374
 

State Of Development

The proposed power management has been modeled and simulated at different channel environments for OFDM-based wireless communication systems.

Contact

Learn About UC TechAlerts - Save Searches and receive new technology matches

Inventors

  • Abdelghaffar, Muhammad
  • Eltawil, Ahmed M.
  • Hussien, Amr M.A.
  • Khajeh, Amin
  • Kurdahi, Fadi J.

Other Information

Keywords

Low power, Wireless communication, Power management, Embedded memories, Fault tolerant, SRAM

Categorized As

  • AN INTEGRAL PART OF
  • Institute for Innovation Logo
  • Institute for Innovation Logo

University of California, Irvine Invention Transfer Group
5141 California Avenue, Suite 200, Irvine,CA 92697-7700
Tel: 949.824.2683 | Fax: 949.824.3880
www.ota.uci.edu | ota@uci.edu

© 2013 - 2017, The Regents of the University of California
Terms of use | Privacy Notice