A new technique for integrating ultra-low loss waveguides (ULLWs) with active silicon and/or compound semiconductor waveguides on a common substrate.
Silicon photonics and its integration with well-known CMOS fabrication technology have the potential to solve inevitable speed bottlenecks in future computing and chip platforms. UCSB’s iPHOD group has developed a unique approach to create ultra-low loss waveguides (ULLWs) using extremely thin silicon nitride cores and thermally grown SiO2 layers, resulting in waveguides with low confinement, low effective index and ultra-low loss values below 0.1 dB/m. Current approaches to integrate these ULLW layers with active photonics layers (where silica waveguides are deposited on top of an active silicon layer) are not possible because the fabrication technology proposed is not directly compatible with ULLW technology, due to the limited thickness of the lower cladding area and its inability to withstand the high heat of the ULLW process.
Researchers at the University of California, Santa Barbara have discovered a new technique for integrating ultra-low loss waveguides (ULLWs) with active silicon and/or compound semiconductor waveguides on a common substrate. By adding the silicon photonic layer through a back-end process, this new approach guarantees thermal-budget, stress-budget, and lower cladding thickness compatibility, and preserves the single-crystalline nature and tight thickness tolerance of a silicon-on-insulator (SOI) waveguide layer. This technique is important for producing high-quality silicon devices and further integrating III-V materials on top of silicon layers. This technique is also well suited for applications such as optical telecommunications and data communications.
|United States Of America||Issued Patent||9,285,540||03/15/2016||2013-142|
waveguides, photonics, silicon, cenIEE, indtelecom, indmicroelec