A Zero-Voltage-Switching Counter Based Outphasing Power Amplifier

Tech ID: 22576 / UC Case 2012-053-0


UCLA researchers in the Department of Electrical Engineering have created a power amplifier (PA) that efficiently generates high power, wide bandwidth modulated radio frequency signals from low voltage supplies while maintaining high linearity.


The increasing sophistication of wireless communication technologies, in particular power conscious portable devices, has made efficient, wide bandwidth, linear power amplifiers (PAs) that handle high peak-to-average signal power ratios critically important. Generally, PAs are the major consuming blocks in any transmitter chain and they alone account for about 70-80% of total power consumption in transmitter chips. Further, wireless communication technologies are increasingly using non-constant envelope modulation schemes for accommodating high data rates in low bandwidths. Designing a PA which can maintain close to peak efficiency over the wide dynamic range of such modulation schemes and also achieve power control is imperative to conserve battery power.


Researchers at UCLA have developed a parallel class-E modified Chireix outphasing power amplifier (PA) that can maintain high efficiency across a wide output power range. The novel architecture essentially implements a zero voltage switching contour-based PA using a modified Chireix outphasing structure. The PA maintains high efficiency for approximately 9-dB back-off of output power and beyond the 9-dB range a simple outphasing is used to extend the dynamic range up to approximately 30 dB.


Power amplifiers in wireless communication systems


  • Maintains constant drain efficiency over a wide dynamic range
  • Allows for wide modulation bandwidths
  • Allows for conservation of batter power in mobile devices
  • Significantly alleviates the envelope-phase mismatch problem common to polar architectures

State Of Development

Researchers have verified the novel PA using realistic transistor level circuit simulation in 0.13μm CMOS. Further, realistic models for passives obtained from AISTIC have been used in the simulations. The proposed PA, implemented using discrete components on an FR4 printed circuit board, achieves a dynamic range of 30 dB with a peak power of 29 dBm and a peak drain efficiency of 65% at about 6-dB back-off from the peak output power at 100 MHz from a 3-V supply.

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 8,890,618 11/18/2014 2012-053


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  • Pamarti, Sudhakar

Other Information


Peak-to-average power ratio, power amplifier (PA), zero voltage switching (ZVS)

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