Researchers at UC San Diego have invented a resistless projection lithographic method to generate three-dimensional patterns on silicon substrates. A porous silicon layer is formed first by projecting an image or test pattern onto a silicon substrate during standard electrochemical etching. The porous layer is then removed in a wet etch revealing a 3-D image or test pattern in micrometer resolution. This technique does not involve the use of complicated, multi-step lithography or mask aligners. It is also quick; a multilayered master can be made from a computer design in less than 60 minutes. Feature sizes of 70 microns have been demonstrated, but smaller features should be possible.
A wide variety of fields, such as sensors, microfluidics, microanalysis, MEMS, and cell biology might benefit from this invention.
|United States Of America||Issued Patent||7,433,811||10/07/2008||2002-144|