Hybrid Network-On-Chip Design with RF Interconnects for Chip Multiprocessors (CMPs)

Summary

Scientists at UCLA in the Computer Science and Electrical Engineering Departments have designed a hybrid network of RF interconnects and traditional mesh architectures for advanced network-on-chip (NoC) communications for chip multiprocessors.

Background

The continued scaling of CMOS devices and the transition to multiple processing cores increases the amount of on-chip interconnects that are required for inter-core communications. Repeated RC wires or RC wire based NoC provide current on-chip communications. However, the RC wires scale poorly and result in increased latency and power consumption.

Innovation

Researchers at UCLA have demonstrated that hybridizing RF interconnects (RF-I) into RC wire based network-on-chip (NoC) designs for chip multi-processors (CMPs) allows significant acceleration of communication, decreased power consumption, and great amount of flexibility for compile-time or runtime reconfiguration of NoC topology for communication optimization.

Applications

• Global interconnects for network-on-chip(NoC) communications
• Chip multi-processor (CMP) communications
• On-chip and off-chip communications

Advantages

• Use of RF-I overcomes limitations of traditional repeated RC wire communications
• Enables high bandwidth, low latency, and low energy consumption
• Application-specific reconfiguration of NoC designs

State of Development

Plans to implement a RF-I NoC prototype chip.

Related Materials

• M. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher and S.W. Tam, CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect, The 14th International Symposium on High-Performance Computer Architecture, Salt Lake City, UT, February 2008 - [more]
• M.-C. F. Chang, E. Socher, S.-W. Tam, J. Cong, and G. Reinman, RF Interconnects for Communications On-chip, Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 78-83, April 2008 - [more]

Patent Status