Nano-electro-mechanical Non-volatile Memory (nemory)

Tech ID: 17609 / UC Case 2006-040-0


By the year 2018, MOSFET gate lengths for logic applications are expected to be scaled below l0nm with operating voltages below 1V. However, flash memory transistors are more difficult to scale because of the thick gate-stack equivalent oxide thickness (EOT) requirements for charge storage (threshold voltage shift) and retention.

Although advanced transistor structures can be leveraged to improve gate-length scalability, high program/erase voltages are still required for fast operation. Thus, alternative integrated-circuit memory technologies such as magnetic RAM (MRAM) and phase-change memory (PCM) have been heavily investigated in recent years. These alternative memory technologies require new materials which increases process complexity and hence cost. In addition, their scalability to sub-10nm cell size is not assured. Therefore, there is a need for a new non-volatile memory technology that can be as scalable (in size and operating voltage) to match the scaling of logic devices.

Researchers at UC Berkeley have developed a new design for nano-scale non-volatile memory. The design fabrication utilizes standard CMOS materials and processes. It leverages established surface micromachining technology and MEMS to achieve an elegantly simple and scalable memory cell structure that can potentially operate with very low voltage levels. The design is ideally suited for use in cross-point memory arrays for very high density non-volatile storage.


Flash memory, storage, RAM


Uses standard CMOS materials and processes, scaleable, low voltage levels, high density, three dimensional fabrication

Patent Status

Country Type Number Dated Case
United States Of America Issued Patent 7,839,710 11/23/2010 2006-040


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Other Information


data storage, semiconductor, MEMS: structure, digital circuits: memory, assembly and packaging, computer

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